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公开(公告)号：US20170270851A1
公开(公告)日：2017-09-21
申请号：US15503051
申请日：2016-08-04
发明人： Guangliang Shang , Seungwoo Han , Zhihe Jin , Mingfu Han , Xing Yao , Haoling Zheng , Yunsil IM , Seungmin Lee , Haijun Qiu , Jungmok Jun , Xue Dong
IPC分类号： G09G3/20
CPC分类号： G09G3/2092 , G09G3/3266 , G09G3/3677 , G09G2310/0286 , G09G2310/0289 , G09G2310/08 , G11C19/28
摘要： A shift register is disclosed including an input module, an output module, a first reset module, a first pull-down module and a second pull-down module. The first pull-down module is configured to supply a reference signal to a first node and an output terminal in response to an active level of a first control signal. The second pull-down module is configured to supply the reference signal to the first node and the output terminal in response to an active level of a second control signal. The active levels of the first control signal and the second control signal occur alternately. Also disclosed are a gate driver circuit and a display apparatus.
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公开(公告)号：US10096374B2
公开(公告)日：2018-10-09
申请号：US15539220
申请日：2016-11-01
发明人： Guangliang Shang , Seungwoo Han , Haoliang Zheng , Xing Yao , Mingfu Han , Hyunsic Choi , Yunsik Im , Yinglong Huang , Jungmok Jun , Xue Dong
摘要： The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.
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公开(公告)号：US10002675B2
公开(公告)日：2018-06-19
申请号：US15504119
申请日：2016-08-12
发明人： Haoliang Zheng , Seungwoo Han , Xing Yao , Hyunsic Choi , Guangliang Shang , Mingfu Han , Yunsik Im , Jungmok Jun , Xue Dong
CPC分类号： G11C19/28 , G09G3/20 , G09G3/3677 , G09G3/3688 , G09G2310/0267 , G09G2310/0286 , G11C19/184 , H01L27/1222 , H01L27/124 , H01L27/1251
摘要： The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.
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4.发明授权公开(公告)号：US10217391B2
公开(公告)日：2019-02-26
申请号：US15541639
申请日：2016-09-18
发明人： Guangliang Shang , Xing Yao , Seungwoo Han , Yujie Gao , Yuanbo Zhang , Ming Chen , Jungmok Jun , Xue Dong
IPC分类号： G11C19/28 , G09G3/32 , G09G3/36 , G09G3/20 , G09G3/3266
摘要： Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage.
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公开(公告)号：US10192504B2
公开(公告)日：2019-01-29
申请号：US15501265
申请日：2016-07-01
发明人： Mingfu Han , Seungwoo Han , Guangliang Shang , Hyunsic Choi , Xing Yao , Haoliang Zheng , Xue Dong , Jungmok Jun , Yunsik Im
摘要： The present disclosure provides a shift register, including: an input unit, an output control unit, a first pull-down unit, a second pull-down unit, a reset unit, and a pull-down control unit. The input unit comprises a control terminal connected to a signal input terminal, a first terminal connected to a first voltage terminal, and a second terminal connected to a first node. The output control unit comprises a control terminal connected to the first node, a first terminal connected to a first clock signal terminal, and a second terminal connected to a signal output terminal. The first pull-down unit comprises a control terminal connected to a second node, a first terminal connected to the first node, and a second terminal connected to a compensation signal terminal. The second pull-down unit comprises a control terminal connected to the compensation signal terminal, and a first terminal connected to the second node.
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6.发明申请公开(公告)号：US20180204494A1
公开(公告)日：2018-07-19
申请号：US15541639
申请日：2016-09-18
发明人： Guangliang Shang , Xing Yao , Seungwoo Han , Yujie Gao , Yuanbo Zhang , Ming Chen , Jungmok Jun , Xue Dong
CPC分类号： G09G3/20 , G09G3/3266 , G09G3/3677 , G09G2300/0408 , G09G2310/0267 , G09G2310/0286 , G11C19/28 , G11C19/287
摘要： Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage.
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