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40 条记录 (耗时 0.031 秒)

    Circuit for providing clock signals with low skew
    11.
    发明授权
    Circuit for providing clock signals with low skew 有权
    提供低偏移时钟信号的电路

    公开(公告)号：US06731142B1

    公开(公告)日：2004-05-04

    申请号：US10412705

    申请日：2003-04-10

    申请人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

    发明人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

    IPC分类号： H03K2100

    CPC分类号： H03M9/00 ,  G06F1/08 ,  H03K5/135

    摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.

    摘要翻译： 公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。 时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。 在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。 移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。 来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。 延迟电路延迟输入参考时钟。 在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。 由于所有输出路径中的延迟相匹配，所以偏斜最小化。

    Circuit for providing clock signals with low skew
    13.
    发明授权
    Circuit for providing clock signals with low skew 有权
    提供低偏移时钟信号的电路

    公开(公告)号：US06549045B1

    公开(公告)日：2003-04-15

    申请号：US10043620

    申请日：2002-01-11

    申请人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

    发明人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

    IPC分类号： H03K2100

    CPC分类号： H03M9/00 ,  G06F1/08 ,  H03K5/135

    摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.

    摘要翻译： 公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。 时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。 在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。 移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。 来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。 延迟电路延迟输入参考时钟。 在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。 由于所有输出路径中的延迟相匹配，所以偏斜最小化。

    Programmable I/O element circuit for high speed logic devices
    14.
    发明授权
    Programmable I/O element circuit for high speed logic devices 有权
    用于高速逻辑器件的可编程I / O元件电路

    公开(公告)号：US07098690B2

    公开(公告)日：2006-08-29

    申请号：US11025774

    申请日：2004-12-29

    申请人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    发明人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： C07K16/28 ,  A61K2039/505 ,  C07K14/47

    摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

    摘要翻译： 用于逻辑阵列的I / O端子的可编程I / O元件适用于根据高速I / O模式（如双数据速率和零总线周转）进行工作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。 另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。 对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块为输出缓冲器的选通输入提供使能信号。 可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

    Configurable decoder for addressing a memory
    16.
    发明授权
    Configurable decoder for addressing a memory 有权
    用于寻址存储器的可配置解码器

    公开(公告)号：US06747903B1

    公开(公告)日：2004-06-08

    申请号：US10046939

    申请日：2002-01-14

    申请人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong ,  Tzung-Chin Chang

    发明人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong ,  Tzung-Chin Chang

    IPC分类号： G11C700

    CPC分类号： H03K19/1776 ,  G11C8/16

    摘要： Methods and apparatus for decoding addresses in a memory to provide mixed input and output data widths. A method includes receiving an address portion comprising a first number of bits. A second number of bits of the address portion are blocked, where the second number is less than the first number. A third number of bits are not blocked, and the third number plus the second number equal the first number. The third number of bits are decoded and a fourth number of memory cells are selected. The fourth number is equal to two to the power of the second number. A fourth number of data bits are received and multiplexed to the selected memory cells. The data bits are written to the selected memory cells.

    摘要翻译： 用于解码存储器中的地址以提供混合的输入和输出数据宽度的方法和装置。 一种方法包括接收包括第一位数的地址部分。 地址部分的第二位数被阻塞，其中第二个数字小于第一个数字。 第三个位数不被阻塞，第三个数字加上第二个数字等于第一个数字。 第三位数被解码，并且选择第四数量的存储单元。 第四个数字等于第二个数字的两倍。 接收第四数量的数据位并将其多路复用到选择的存储单元。 数据位被写入选定的存储单元。

    Programmable I/O element circuit for high speed logic devices
    18.
    发明申请
    Programmable I/O element circuit for high speed logic devices 有权
    用于高速逻辑器件的可编程I / O元件电路

    公开(公告)号：US20050162187A1

    公开(公告)日：2005-07-28

    申请号：US11025774

    申请日：2004-12-29

    申请人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    发明人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    IPC分类号： C07K14/47 ,  C07K16/28 ,  H03K19/177

    CPC分类号： C07K16/28 ,  A61K2039/505 ,  C07K14/47

    摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

    摘要翻译： 用于逻辑阵列的I / O端子的可编程I / O元件适用于根据双速数据速率和零总线周转等高速I / O模式进行工作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。 另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。 对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块为输出缓冲器的选通输入提供使能信号。 可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

    Schmitt trigger circuit with adjustable trip point voltages
    19.
    发明授权
    Schmitt trigger circuit with adjustable trip point voltages 有权
    施密特触发电路具有可调跳闸点电压

    公开(公告)号：US06870413B1

    公开(公告)日：2005-03-22

    申请号：US10017933

    申请日：2001-12-14

    申请人： Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Yan Chong ,  Xiaobao Wang ,  Philip Pan ,  Gopinath Rangan ,  In Whan Kim

    发明人： Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Yan Chong ,  Xiaobao Wang ,  Philip Pan ,  Gopinath Rangan ,  In Whan Kim

    IPC分类号： H03K3/3565 ,  H03K3/012

    CPC分类号： H03K3/3565

    摘要： A Schmitt trigger circuit has an adjustable hysteresis characteristic by providing a plurality of feedback circuits that differently affect at least one, and preferably both, of the circuit's upper trip point level and lower trip point level. The upper trip point level can be adjusted by selecting a desired feedback circuit from a first set of feedback circuits, and/or the lower trip point level can be adjusted by selecting a desired feedback circuit from a second set of feedback circuits. Feedback circuit selection is achieved by one or more control signals that may be programmable. The hysteresis characteristic can be adjusted to meet desired noise margin, delay, and input recognition criteria at different VCC levels. The Schmitt trigger circuit may be a CMOS Schmitt trigger with two input stage NMOS, two input stage PMOS transistors, a first set of NMOS feedback circuits, and a second set of PMOS feedback circuits.

    摘要翻译： 施密特触发电路具有可调滞后特性，通过提供多个反馈电路，其不同地影响电路的上跳点电平和较低跳变点电平的至少一个，优选两者。 可以通过从第一组反馈电路中选择所需的反馈电路来调整上跳点电平，和/或可以通过从第二组反馈电路中选择所需的反馈电路来调整下跳变点电平。 反馈电路选择由一个或多个可编程的控制信号来实现。 可以调节滞后特性，以满足不同VCC电平下的所需噪声容限，延迟和输入识别准则。 施密特触发电路可以是具有两个输入级NMOS，两个输入级PMOS晶体管，第一组NMOS反馈电路组和第二组PMOS反馈电路的CMOS施密特触发器。