公开(公告)号：US07078255B2

公开(公告)日：2006-07-18

申请号：US10933545

申请日：2004-09-03

申请人： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

发明人： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/949

摘要： Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

公开(公告)号：US20050023534A1

公开(公告)日：2005-02-03

申请号：US10933545

申请日：2004-09-03

申请人： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

发明人： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

IPC分类号： G09F9/30 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/417 ,  H01L29/786 ,  H01L29/04 ,  H01L31/036

CPC分类号： G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/949

摘要： Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

摘要翻译： 制造液晶显示器的简化方法。 通过使用第一掩模在基板上形成包括栅极线，栅极焊盘和栅电极的栅极线。 依次沉积栅极绝缘层，半导体层，欧姆接触层和金属层以制成四层，并通过使用第二掩模的干蚀刻图案化。 此时，四层被图案化以具有网状布局的矩阵并覆盖栅极线。 在显示区域形成露出基板的开口，在周边区域形成露出栅极焊盘的接触孔。 接下来，沉积ITO并且涂覆在ITO上的光致抗蚀剂层。 然后，通过使用第三掩模和干蚀刻对ITO层进行图案化，并且数据导体层和未被ITO层覆盖的欧姆接触层被干蚀刻。 在沉积钝化层之后，通过使用第四掩模形成开口，并蚀刻通过开口的暴露的半导体层以将相邻数据线下的半导体层分离。

公开(公告)号：US06787809B2

公开(公告)日：2004-09-07

申请号：US10644917

申请日：2003-08-21

申请人： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

发明人： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

IPC分类号： H01L2904

CPC分类号： G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/949

摘要： Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

摘要翻译： 制造液晶显示器的简化方法。 通过使用第一掩模在基板上形成包括栅极线，栅极焊盘和栅电极的栅极线。 依次沉积栅极绝缘层，半导体层，欧姆接触层和金属层以制成四层，并通过使用第二掩模的干蚀刻图案化。 此时，四层被图案化以具有网状布局的矩阵并覆盖栅极线。 在显示区域形成露出基板的开口，在周边区域形成露出栅极焊盘的接触孔。 接下来，沉积ITO并且涂覆在ITO上的光致抗蚀剂层。 然后，通过使用第三掩模和干蚀刻对ITO层进行图案化，并且数据导体层和未被ITO层覆盖的欧姆接触层被干蚀刻。 在沉积钝化层之后，通过使用第四掩模形成开口，并蚀刻通过开口的暴露的半导体层以将相邻数据线下的半导体层分离。

公开(公告)号：US06642074B2

公开(公告)日：2003-11-04

申请号：US10172982

申请日：2002-06-18

申请人： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

发明人： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

IPC分类号： H01L2100

CPC分类号： G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/949

摘要： Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

摘要翻译： 制造液晶显示器的简化方法。 通过使用第一掩模在基板上形成包括栅极线，栅极焊盘和栅电极的栅极线。 依次沉积栅极绝缘层，半导体层，欧姆接触层和金属层以制成四层，并通过使用第二掩模的干蚀刻图案化。 此时，四层被图案化以具有网状布局的矩阵并覆盖栅极线。 在显示区域形成露出基板的开口，在周边区域形成露出栅极焊盘的接触孔。 接下来，沉积ITO并且涂覆在ITO上的光致抗蚀剂层。 然后，通过使用第三掩模和干蚀刻对ITO层进行图案化，并且数据导体层和未被ITO层覆盖的欧姆接触层被干蚀刻。 在沉积钝化层之后，通过使用第四掩模形成开口，并蚀刻通过开口的暴露的半导体层以将相邻数据线下的半导体层分离。

公开(公告)号：US06429057B1

公开(公告)日：2002-08-06

申请号：US09410760

申请日：1999-10-01

申请人： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

发明人： Mun-Pyo Hong ,  Woon-Yong Park ,  Jong-Soo Yoon

IPC分类号： H01L2100

CPC分类号： G02F1/13458 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/949

摘要： Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

摘要翻译： 制造液晶显示器的简化方法。 通过使用第一掩模在基板上形成包括栅极线，栅极焊盘和栅电极的栅极线。 依次沉积栅极绝缘层，半导体层，欧姆接触层和金属层以制成四层，并通过使用第二掩模的干蚀刻图案化。 此时，四层被图案化以具有网状布局的矩阵并覆盖栅极线。 在显示区域形成露出基板的开口，在周边区域形成露出栅极焊盘的接触孔。 接下来，沉积ITO并且涂覆在ITO上的光致抗蚀剂层。 然后，通过使用第三掩模和干蚀刻对ITO层进行图案化，并且数据导体层和未被ITO层覆盖的欧姆接触层被干蚀刻。 在沉积钝化层之后，通过使用第四掩模形成开口，并蚀刻通过开口的暴露的半导体层以将相邻数据线下的半导体层分离。

公开(公告)号：US06445004B1

公开(公告)日：2002-09-03

申请号：US09617311

申请日：2000-07-14

申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

IPC分类号： H01L2904

CPC分类号： G02F1/136286 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.

摘要翻译： Mo或MoW组合物层具有小于15μOMEGAcm的低电阻率，并且使用Al合金附魔或Cr附魔被蚀刻成具有平滑的锥角，并且Mo或MoW层用于显示器或 半导体显示器以及Al层或Cr层。 由于通过调节沉积压力可以沉积Mo或MoW层以便对基底施加低应力，所以可以单独使用单个MoW层作为布线。 当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，使用CF 4 + O 2的蚀刻气体系统可以防止Mo或MoW合金层的蚀刻，以及蚀刻气体 SF6 + HCl（+ He）或SF6 + Cl2（+ He）可以形成要平滑的接触孔的边缘轮廓。 此外，当使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用采用诸如卤化氢和至少一种选自CF 4，CHF 3的气体的气体的蚀刻气体系统， CHClF 2，CH 3 F和C 2 F 6，产生良好的TFT特性，并且H 2等离子体处理可以进一步提高TFT特性。

公开(公告)号：US06686606B2

公开(公告)日：2004-02-03

申请号：US10389778

申请日：2003-03-18

申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chua-Gi You

发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chua-Gi You

IPC分类号： H01L2904

CPC分类号： G02F1/136286 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.

公开(公告)号：US06582982B2

公开(公告)日：2003-06-24

申请号：US09962210

申请日：2001-09-26

申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

IPC分类号： H01L2100

CPC分类号： G02F1/1368 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.

公开(公告)号：US06486494B2

公开(公告)日：2002-11-26

申请号：US10035245

申请日：2002-01-04

申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

IPC分类号： H01L2904

CPC分类号： G02F1/136286 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with An Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.

摘要翻译： Mo或MoW组合物层具有小于15μOMEGAcm的低电阻率，并且使用Al合金附魔或Cr附魔被蚀刻成具有平滑的锥角，并且Mo或MoW层用于显示器或 半导体显示器以及Al Al层或Cr层。 由于通过调节沉积压力可以沉积Mo或MoW层以便对基底施加低应力，所以可以单独使用单个MoW层作为布线。 当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，使用CF 4 + O 2的蚀刻气体系统可以防止Mo或MoW合金层的蚀刻，以及蚀刻气体 SF6 + HCl（+ He）或SF6 + Cl2（+ He）可以形成要平滑的接触孔的边缘轮廓。 此外，当使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用采用诸如卤化氢和至少一种选自CF 4，CHF 3的气体的气体的蚀刻气体系统， CHClF 2，CH 3 F和C 2 F 6，产生良好的TFT特性，并且H 2等离子体处理可以进一步提高TFT特性。

公开(公告)号：US06380098B1

公开(公告)日：2002-04-30

申请号：US09492830

申请日：2000-01-27

申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

IPC分类号： H01L21302

CPC分类号： G02F1/1368 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： The Mo or MoW composition layer has the low resistivity less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy etchant or a Cr etchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor device along with an Al layer and a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using a polymer layer, an etch gas system CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched by using the Mo or MoW layer as a mask, to use an etch gas system such as hydrogen halide and at least one selected from CF4, CHF3, CHClF2, CH3F and C2F6 yield the good characteristics of TFT, and H2 plasma treatment can cause the characteristics of the TFT to be improved.

摘要翻译： Mo或MoW组合物层具有小于15μOMEGAcm的低电阻率，并且使用Al合金蚀刻剂或Cr蚀刻剂蚀刻以具有平滑的锥角，并且Mo或MoW层用于显示器或半导体的布线 装置以及Al层和Cr层。 由于可以通过调整沉积压力来沉积Mo或MoW层以对基底施加低应力，所以可以单个MoW层自身用作布线。 当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，蚀刻气体系统CF4 + O2可以防止Mo或MoW合金层的蚀刻，并且蚀刻气体SF6 + HCl（+ He）或SF6 + Cl2（+ He）可以形成要平滑的接触孔的边缘轮廓。 此外，当通过使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用蚀刻气体系统如卤化氢和选自CF 4，CHF 3，CHClF 2，CH 3 F 和C2F6产生TFT的良好特性，并且H2等离子体处理可以导致TFT的特性得到改善。