利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

134 条记录 (耗时 0.058 秒)

    Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof
    2.
    发明授权
    Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof 有权
    配线用组合物，使用该组合物的布线及其制造方法，使用布线的显示器及其制造方法

    公开(公告)号：US06445004B1

    公开(公告)日：2002-09-03

    申请号：US09617311

    申请日：2000-07-14

    申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

    发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

    IPC分类号： H01L2904

    CPC分类号： G02F1/136286 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.

    摘要翻译： Mo或MoW组合物层具有小于15μOMEGAcm的低电阻率，并且使用Al合金附魔或Cr附魔被蚀刻成具有平滑的锥角，并且Mo或MoW层用于显示器或 半导体显示器以及Al层或Cr层。 由于通过调节沉积压力可以沉积Mo或MoW层以便对基底施加低应力，所以可以单独使用单个MoW层作为布线。 当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，使用CF 4 + O 2的蚀刻气体系统可以防止Mo或MoW合金层的蚀刻，以及蚀刻气体 SF6 + HCl（+ He）或SF6 + Cl2（+ He）可以形成要平滑的接触孔的边缘轮廓。 此外，当使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用采用诸如卤化氢和至少一种选自CF 4，CHF 3的气体的气体的蚀刻气体系统， CHClF 2，CH 3 F和C 2 F 6，产生良好的TFT特性，并且H 2等离子体处理可以进一步提高TFT特性。

    Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof
    4.
    发明授权
    Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof 有权
    配线用组合物，使用该组合物的布线及其制造方法，使用布线的显示器及其制造方法

    公开(公告)号：US06486494B2

    公开(公告)日：2002-11-26

    申请号：US10035245

    申请日：2002-01-04

    申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

    发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

    IPC分类号： H01L2904

    CPC分类号： G02F1/136286 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with An Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.

    摘要翻译： Mo或MoW组合物层具有小于15μOMEGAcm的低电阻率，并且使用Al合金附魔或Cr附魔被蚀刻成具有平滑的锥角，并且Mo或MoW层用于显示器或 半导体显示器以及Al Al层或Cr层。 由于通过调节沉积压力可以沉积Mo或MoW层以便对基底施加低应力，所以可以单独使用单个MoW层作为布线。 当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，使用CF 4 + O 2的蚀刻气体系统可以防止Mo或MoW合金层的蚀刻，以及蚀刻气体 SF6 + HCl（+ He）或SF6 + Cl2（+ He）可以形成要平滑的接触孔的边缘轮廓。 此外，当使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用采用诸如卤化氢和至少一种选自CF 4，CHF 3的气体的气体的蚀刻气体系统， CHClF 2，CH 3 F和C 2 F 6，产生良好的TFT特性，并且H 2等离子体处理可以进一步提高TFT特性。

    Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof
    5.
    发明授权
    Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof 有权
    配线用组合物，使用该组合物的布线及其制造方法，使用布线的显示器及其制造方法

    公开(公告)号：US06380098B1

    公开(公告)日：2002-04-30

    申请号：US09492830

    申请日：2000-01-27

    申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

    发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

    IPC分类号： H01L21302

    CPC分类号： G02F1/1368 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The Mo or MoW composition layer has the low resistivity less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy etchant or a Cr etchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor device along with an Al layer and a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using a polymer layer, an etch gas system CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched by using the Mo or MoW layer as a mask, to use an etch gas system such as hydrogen halide and at least one selected from CF4, CHF3, CHClF2, CH3F and C2F6 yield the good characteristics of TFT, and H2 plasma treatment can cause the characteristics of the TFT to be improved.

    摘要翻译： Mo或MoW组合物层具有小于15μOMEGAcm的低电阻率，并且使用Al合金蚀刻剂或Cr蚀刻剂蚀刻以具有平滑的锥角，并且Mo或MoW层用于显示器或半导体的布线 装置以及Al层和Cr层。 由于可以通过调整沉积压力来沉积Mo或MoW层以对基底施加低应力，所以可以单个MoW层自身用作布线。 当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，蚀刻气体系统CF4 + O2可以防止Mo或MoW合金层的蚀刻，并且蚀刻气体SF6 + HCl（+ He）或SF6 + Cl2（+ He）可以形成要平滑的接触孔的边缘轮廓。 此外，当通过使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用蚀刻气体系统如卤化氢和选自CF 4，CHF 3，CHClF 2，CH 3 F 和C2F6产生TFT的良好特性，并且H2等离子体处理可以导致TFT的特性得到改善。

    Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof
    6.
    发明授权
    Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof 失效
    配线用组合物，使用该组合物的布线及其制造方法，使用布线的显示器及其制造方法

    公开(公告)号：US06946681B2

    公开(公告)日：2005-09-20

    申请号：US10732480

    申请日：2003-12-11

    申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

    发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

    IPC分类号： G02F1/1362 ,  G02F1/1368 ,  H01L21/28 ,  H01L23/482 ,  H01L29/423 ,  H01L29/49 ,  H01L29/04 ,  H01L31/036 ,  H01L31/0376

    CPC分类号： G02F1/136286 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The Mo or MoW composition layer has a low resistivity of less than 15 μΩcm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.

    摘要翻译： Mo或MoW组合物层具有小于15μOggacm的低电阻率，并且使用Al合金附魔或Cr附魔蚀刻成具有平滑的锥角，并且Mo或MoW层用于显示器或 半导体显示器以及Al层或Cr层。 由于通过调节沉积压力可以沉积Mo或MoW层以便对基底施加低应力，所以可以单独使用单个MoW层作为布线。 当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，使用CF 4 O 2 O 2的蚀刻气体系统 防止Mo或MoW合金层的蚀刻，以及SF 6+ + HCl（+ He）或SF 6 + Cl 2 2的蚀刻气体 >（+ He）可以形成要平滑的接触孔的边缘轮廓。 此外，当使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用采用诸如卤化氢的气体和选自以下的至少一种气体的蚀刻气体系统： 4，CHF 3，CHClF 2，CH 3，F和C 2 6 ，产生良好的TFT特性，H 2等离子体处理可进一步提高TFT特性。

    Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same
    8.
    发明授权
    Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same 有权
    用于液晶显示器的薄膜晶体管阵列面板及其制造方法

    公开(公告)号：US06524876B1

    公开(公告)日：2003-02-25

    申请号：US09545891

    申请日：2000-04-07

    申请人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

    发明人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

    IPC分类号： H01L2100

    CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

    摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.

    摘要翻译： 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。 接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。 此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。 接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

    Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same
    10.
    发明申请
    Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same 有权
    用于液晶显示器的薄膜晶体管阵列面板及其制造方法

    公开(公告)号：US20050170592A1

    公开(公告)日：2005-08-04

    申请号：US11080612

    申请日：2005-03-16

    申请人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

    发明人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

    IPC分类号： G02F1/1362 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L31/0376

    CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

    摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.

    摘要翻译： 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。 接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。 此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。 接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。