公开(公告)号：US06903460B2

公开(公告)日：2005-06-07

申请号：US10689060

申请日：2003-10-21

申请人： Yutaka Fukuda ,  Hirofumi Abe ,  Yoshinori Arashima ,  Shigeki Takahashi

发明人： Yutaka Fukuda ,  Hirofumi Abe ,  Yoshinori Arashima ,  Shigeki Takahashi

IPC分类号： H01L21/3205 ,  H01L23/482 ,  H01L23/52 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L23/48

CPC分类号： H01L29/7816 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/41758 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor equipment includes a semiconductor substrate, a plurality of transistors having a source cell and a drain cell disposed alternately on the substrate, and upper and lower layer wirings for electrically connecting the source cells and the drain cells. The lower layer wiring includes a first source wiring for connecting the neighboring source cells and a first drain wiring for connecting the neighboring drain cells. The upper layer wiring includes a second source wiring for connecting to the first source wiring and a second drain wiring for connecting to the first drain wiring. A width of the second source wiring is wider than that of the first source wiring, and a width of the second drain wiring is wider than that of the first drain wiring. The second source wiring and the second drain wiring are disposed alternately.

摘要翻译： 半导体设备包括半导体衬底，具有交替放置在衬底上的源极单元和漏极单元的多个晶体管，以及用于电连接源极单元和漏极单元的上部和下部布线。 下层布线包括用于连接相邻源极单元的第一源极布线和用于连接相邻漏极单元的第一漏极布线。 上层布线包括用于连接到第一源极布线的第二源极布线和用于连接到第一漏极布线的第二漏极布线。 第二源极布线的宽度比第一源极布线的宽度宽，并且第二漏极布线的宽度比第一漏极布线的宽度宽。 第二源极配线和第二漏极配线交替配置。

公开(公告)号：US06794921B2

公开(公告)日：2004-09-21

申请号：US10616426

申请日：2003-07-09

申请人： Hirofumi Abe ,  Hideaki Ishihara ,  Shinichi Noda

发明人： Hirofumi Abe ,  Hideaki Ishihara ,  Shinichi Noda

IPC分类号： H03K508

CPC分类号： H03K5/08

摘要： In the clamp circuit, the first transistor shifts a target clamp voltage by a gate-source voltage to output the target clamp voltage. The buffer circuit inputs the shifted voltage and output a reference voltage on the inputted shifted voltage. The gate of the second transistor is connected to the output terminal of the buffer circuit. The source of the second transistor is connected to the input terminal of the first transistor. In this structure, the reference voltage is supplied to the gate of the second transistor so that, when a terminal voltage of the input terminal of the IC is not less than a clamp voltage corresponding to the sum of the reference voltage and a threshold voltage of the second transistor, the second transistor turns on, whereby the terminal voltage is clamped to a clamp voltage related to the target clamp voltage.

摘要翻译： 在钳位电路中，第一晶体管将目标钳位电压移位栅源电压以输出目标钳位电压。 缓冲电路输入移位电压，并输出输入的移位电压的参考电压。 第二晶体管的栅极连接到缓冲电路的输出端。 第二晶体管的源极连接到第一晶体管的输入端。 在该结构中，参考电压被提供给第二晶体管的栅极，使得当IC的输入端子的端电压不小于对应于参考电压和阈值电压之和的钳位电压时 第二晶体管，第二晶体管导通，由此端子电压被钳位到与目标钳位电压相关的钳位电压。

公开(公告)号：US5716864A

公开(公告)日：1998-02-10

申请号：US589583

申请日：1996-01-22

申请人： Hirofumi Abe

发明人： Hirofumi Abe

IPC分类号： H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11534

摘要： A first insulating film for the formation of a gate insulating film is formed on a semiconductor substrate having a memory cell forming region and a peripheral transistor forming region. A first conductive film for the formation of a floating gate is formed on the first insulating film, and a second insulating film is formed on the first conductive film. A second conductive film is formed on the second insulating film for protecting the second insulating film, and a protective film performing the functions of an oxidation-resistant film, a washing-resistant film and an etching resistant film is formed on the second conductive film. Then, the peripheral transistor region is subjected to a predetermined process. A third conductive film, which will become a control gate of the memory cell and a gate of the peripheral transistor, is formed on the second conductive film and the peripheral transistor forming region subjected to the predetermined process.

摘要翻译： 在具有存储单元形成区域和外围晶体管形成区域的半导体衬底上形成用于形成栅极绝缘膜的第一绝缘膜。 在第一绝缘膜上形成用于形成浮栅的第一导电膜，在第一导电膜上形成第二绝缘膜。 在第二绝缘膜上形成用于保护第二绝缘膜的第二导电膜，并且在第二导电膜上形成执行抗氧化膜，耐洗涤膜和耐蚀刻膜的功能的保护膜。 然后，对周边晶体管区域进行预定处理。 在第二导电膜和周边晶体管形成区域形成经过预定处理的第三导电膜，其将成为存储单元的控制栅极和外围晶体管的栅极。

公开(公告)号：US07034616B2

公开(公告)日：2006-04-25

申请号：US10769758

申请日：2004-02-03

申请人： Naoya Tsuchiya ,  Hirofumi Abe ,  Shoichi Okuda

发明人： Naoya Tsuchiya ,  Hirofumi Abe ,  Shoichi Okuda

IPC分类号： H03F3/45

CPC分类号： H03F3/4508 ,  H03F1/52 ,  H03F2200/361 ,  H03F2200/78

摘要： In a circuit according to the present invention, a multi-collector transistor is provided which includes first to third collectors so that, when a current does not flow from the second collector, a current from the first collector increases but a current from the third collector does not vary. When transistors of the circuit turn off because the voltage of an input signal gets out of an in-phase input voltage range, the supply of the current from the second collector comes to a stop and, hence, the current from the first collector increases. In this situation, further transistors carry out their on/off operations, thereby fixing the output of the circuit to a low level. That is, this circuit can, irrespective of poor pair compatibility between the transistors, fix the output logical level to a desired level when the voltage of an input signal gets out of an in-phase input voltage range.

摘要翻译： 在根据本发明的电路中，提供了一种多集电极晶体管，其包括第一至第三集电极，使得当电流不从第二集电极流出时，来自第一集电极的电流增加，但来自第三集电极的电流 没有变化。 当晶体管由于输入信号的电压偏离同相输入电压范围而断开时，来自第二集电极的电流的供应停止，因此来自第一集电极的电流增加。 在这种情况下，进一步的晶体管执行它们的开/关操作，从而将电路的输出固定在低电平。 也就是说，无论晶体管之间的差的对兼容性如何，该电路都可以将输出逻辑电平固定在期望的电平上，当输入信号的电压从同相输入电压范围中脱离时。

公开(公告)号：US06876180B2

公开(公告)日：2005-04-05

申请号：US10292125

申请日：2002-11-11

申请人： Akira Suzuki ,  Hirofumi Abe ,  Hideaki Ishihara

发明人： Akira Suzuki ,  Hirofumi Abe ,  Hideaki Ishihara

IPC分类号： G05F1/56 ,  G05F1/575 ,  G05F1/40 ,  G05F1/44

CPC分类号： G05F1/575

摘要： A reference voltage circuit and an operational amplifier operate when an output voltage is produced from an output terminal of a power supply circuit. When the output voltage is low in the rising phase of a power source voltage, a transistor Q17 in a startup circuit turns on and a transistor Q14 turns off to surely turn on transistors Q11 and Q12. Upon the output voltage exceeding a predetermined level, the transistor Q17 turns off and an ordinary feedback control starts.

摘要翻译： 当从电源电路的输出端产生输出电压时，参考电压电路和运算放大器工作。 当在电源电压的上升相中的输出电压为低时，启动电路中的晶体管Q17导通，晶体管Q14截止，可靠地导通晶体管Q11，Q12。 当输出电压超过预定电平时，晶体管Q17截止，并开始普通的反馈控制。

公开(公告)号：US5855334A

公开(公告)日：1999-01-05

申请号：US874340

申请日：1997-06-13

申请人： Hirofumi Abe ,  Akihisa Inoue ,  Shinichi Takahashi

发明人： Hirofumi Abe ,  Akihisa Inoue ,  Shinichi Takahashi

IPC分类号： G03B27/58 ,  B65D85/671

CPC分类号： G03B27/588 ,  B65D2301/20 ,  Y10S229/93

摘要： A rectangular parallelepipedic case includes four or more walls formed by bending a single plate. To produce the case, a double plate is used. The double plate is formed from plastic by extrusion, and first and second plate elements confronted with each other. Partition portions interconnect the first and second plate elements, and extend in the direction of the extrusion, to define plural hollow chambers between the first and second plate elements. The double plate is bent along bend lines substantially at a right angle. At least one of the bend lines is at least partially curved.

摘要翻译： 长方体壳包括通过弯曲单个板形成的四个或更多个壁。 为了生产这种情况，使用双层板。 双板由塑料通过挤出形成，第一和第二板元件相互面对。 分隔部分将第一和第二板状元件相互连接，并在挤出方向上延伸，以在第一和第二板状元件之间限定多个中空室。 双板基本上以直角弯曲弯曲。 至少一条弯曲线至少部分弯曲。

公开(公告)号：US5846211A

公开(公告)日：1998-12-08

申请号：US805643

申请日：1997-02-27

申请人： Masao Sakaguchi ,  Junichi Yoshiike ,  Hiroaki Tsuruta ,  Hirofumi Abe

发明人： Masao Sakaguchi ,  Junichi Yoshiike ,  Hiroaki Tsuruta ,  Hirofumi Abe

IPC分类号： A61B5/22 ,  A61B5/103

CPC分类号： A61B5/228

摘要： An occlusal force-meter 1 includes an occlusal force detecting portion 2 for detecting an occlusal force and a main body 3 for processing the detected signal obtained by the occlusal force detecting portion 2 to display the occlusal force measured value on a display 4. The occlusal force detecting portion 2 includes a transmitting portion (second pressure transmitting portion) 5 having diaphragm portions 7, 8 at an upper surface and/or a lower surface of one end portion 5f thereof. A pressure medium liquid L is filed therein, for transmitting the occlusal force added to the diaphragm portions 7, 8 to a pressure detector 9 disposed on the other end portion 5r thereof. A first pressure transmitting portion 10 is positioned between teeth T and the diaphragm portions 7, 8 at the time of occlusion of the tested person for adding the occlusal force to surfaces of the diaphragm portions 7, 8 perpendicularly through the pressure applied surfaces of the diaphragm portions 7, 8 perpendicularly through the pressure applied surfaces Fu, Fd abutted to outer surfaces of the diaphragm portions 7, 8.

摘要翻译： 咬合力计1包括用于检测咬合力的咬合力检测部分2和用于处理由咬合力检测部分2获得的检测信号的主体3，以在显示器4上显示咬合力测量值。咬合面 力检测部分2包括在其一个端部5f的上表面和/或下表面处具有隔膜部分7,8的传递部分（第二压力传递部分）5。 压力介质液体L被放置在其中，用于将添加到膜部分7,8上的咬合力传递到设置在其另一端部5r上的压力检测器9。 第一压力传递部分10位于牙齿T和隔膜部分7,8之间，在被测试者闭塞时，通过垂直于隔膜的压力施加表面垂直地向隔膜部分7,8的表面添加咬合力 垂直于压力施加的表面Fu，Fd的部分7,8紧贴在隔膜部分7,8的外表面上。

公开(公告)号：US5444650A

公开(公告)日：1995-08-22

申请号：US188335

申请日：1994-01-25

申请人： Hirofumi Abe ,  Tadashi Shibata

发明人： Hirofumi Abe ,  Tadashi Shibata

IPC分类号： G11C17/16

CPC分类号： G11C17/16

摘要： A programmable semiconductor memory cell is provided; which secures a sufficient output signal voltage margin and which also has reduced current dissipation and improved durability. To program the programmable semiconductor memory cell of this invention, a high write potential is applied to the high-level lead of a fuse and a selector transistor is turned on to blow the fuse. When reading the memory cell, high read potential is applied to the high-level lead of the fuse. Because an emitter and base of an output transistor are connected to both leads of the fuse, the output transistor is turned on when the fuse is blown and is turned off when the fuse is not blown. The output transistor outputs an amplified signal voltage to an output line.

摘要翻译： 提供可编程半导体存储单元; 这确保了足够的输出信号电压裕度，并且还具有减少的电流消耗和改善的耐久性。 为了对本发明的可编程半导体存储单元进行编程，将高写入电位施加到熔丝的高电平引线，并且选择晶体管导通以熔断熔丝。 当读取存储单元时，高电平读取将被施加到保险丝的高电平引线。 因为输出晶体管的发射极和基极连接到熔丝的两个引线，所以当保险丝熔断时，输出晶体管导通，而当熔丝不熔断时，输出晶体管截止。 输出晶体管将放大的信号电压输出到输出线。

公开(公告)号：US08511919B2

公开(公告)日：2013-08-20

申请号：US13367152

申请日：2012-02-06

申请人： Hirofumi Abe

发明人： Hirofumi Abe

IPC分类号： G03B9/02

CPC分类号： G03B9/02 ,  G03B11/00

摘要： A light quantity adjustment device includes: an aperture mechanism that varies an aperture opening through drive of aperture blades to restrict a quantity of light that passes through the aperture opening; and an ND filter inserted in and removed from an optical path on a light incident side or a light exit side of the aperture opening. The ND filter has a distribution of transmittance in which the transmittance differs in a direction of interposition of the ND filter in the optical path of the aperture opening, and includes a recessed portion formed by recessing a center portion of a distal-end region of the ND filter on a side of interposition in the optical path of the aperture opening in a direction opposite the direction of interposition.

摘要翻译： 光量调节装置包括：孔机构，其通过光圈叶片的驱动改变孔径开口，以限制穿过孔口的光量; 以及插入孔径开口的光入射侧或光出射侧的光路中的ND滤光器。 ND滤光器具有透光率的分布，其中透光率在孔径开口的光路中插入ND滤光器的方向不同，并且包括凹部，该凹部通过凹陷部分形成， ND滤光器在与开口方向相反的方向上的光阑开口的光路中的插入侧。

公开(公告)号：US20120201530A1

公开(公告)日：2012-08-09

申请号：US13367152

申请日：2012-02-06

申请人： Hirofumi Abe

发明人： Hirofumi Abe

IPC分类号： G03B9/06

CPC分类号： G03B9/02 ,  G03B11/00

摘要： A light quantity adjustment device includes: an aperture mechanism that varies an aperture opening through drive of aperture blades to restrict a quantity of light that passes through the aperture opening; and an ND filter inserted in and removed from an optical path on a light incident side or a light exit side of the aperture opening. The ND filter has a distribution of transmittance in which the transmittance differs in a direction of interposition of the ND filter in the optical path of the aperture opening, and includes a recessed portion formed by recessing a center portion of a distal-end region of the ND filter on a side of interposition in the optical path of the aperture opening in a direction opposite the direction of interposition.

摘要翻译： 光量调节装置包括：孔机构，其通过光圈叶片的驱动改变孔径开口，以限制穿过孔口的光量; 以及插入孔径开口的光入射侧或光出射侧的光路中的ND滤光器。 ND滤光器具有透光率的分布，其中透光率在孔径开口的光路中插入ND滤光器的方向不同，并且包括凹部，该凹部通过凹陷部分形成， ND滤光器在与开口方向相反的方向上的光阑开口的光路中的插入侧。