公开(公告)号：US07034616B2

公开(公告)日：2006-04-25

申请号：US10769758

申请日：2004-02-03

申请人： Naoya Tsuchiya ,  Hirofumi Abe ,  Shoichi Okuda

发明人： Naoya Tsuchiya ,  Hirofumi Abe ,  Shoichi Okuda

IPC分类号： H03F3/45

CPC分类号： H03F3/4508 ,  H03F1/52 ,  H03F2200/361 ,  H03F2200/78

摘要： In a circuit according to the present invention, a multi-collector transistor is provided which includes first to third collectors so that, when a current does not flow from the second collector, a current from the first collector increases but a current from the third collector does not vary. When transistors of the circuit turn off because the voltage of an input signal gets out of an in-phase input voltage range, the supply of the current from the second collector comes to a stop and, hence, the current from the first collector increases. In this situation, further transistors carry out their on/off operations, thereby fixing the output of the circuit to a low level. That is, this circuit can, irrespective of poor pair compatibility between the transistors, fix the output logical level to a desired level when the voltage of an input signal gets out of an in-phase input voltage range.

摘要翻译： 在根据本发明的电路中，提供了一种多集电极晶体管，其包括第一至第三集电极，使得当电流不从第二集电极流出时，来自第一集电极的电流增加，但来自第三集电极的电流 没有变化。 当晶体管由于输入信号的电压偏离同相输入电压范围而断开时，来自第二集电极的电流的供应停止，因此来自第一集电极的电流增加。 在这种情况下，进一步的晶体管执行它们的开/关操作，从而将电路的输出固定在低电平。 也就是说，无论晶体管之间的差的对兼容性如何，该电路都可以将输出逻辑电平固定在期望的电平上，当输入信号的电压从同相输入电压范围中脱离时。

公开(公告)号：US07268596B2

公开(公告)日：2007-09-11

申请号：US11220529

申请日：2005-09-08

申请人： Kingo Ota ,  Shoichi Okuda ,  Hirofumi Abe

发明人： Kingo Ota ,  Shoichi Okuda ,  Hirofumi Abe

IPC分类号： H03B1/00

CPC分类号： H03K17/04206 ,  H03K17/0822

摘要： A semiconductor device for driving a load includes a first semiconductor switching element interposed between a power supply terminal and a load, a second semiconductor switching element interposed between the load and a ground terminal, a high-side driver, a low-side driver, and a voltage regulator. The voltage regulator reduces a voltage applied to a control terminal of the second switching element, when a voltage of a load terminal of the second switching element is lower than a predetermined voltage. Then, a voltage applied between the load terminal and the ground terminal of the second switching element increases, and accordingly a voltage applied between the power supply terminal and the load terminal of the first switching element decreases.

摘要翻译： 用于驱动负载的半导体装置包括插入在电源端子和负载之间的第一半导体开关元件，插入在负载和接地端子之间的第二半导体开关元件，高侧驱动器，低侧驱动器和 电压调节器。 当第二开关元件的负载端子的电压低于预定电压时，电压调节器减小施加到第二开关元件的控制端子的电压。 然后，施加在第二开关元件的负载端子和接地端子之间的电压增加，因此施加在第一开关元件的电源端子和负载端子之间的电压降低。

公开(公告)号：US20060087348A1

公开(公告)日：2006-04-27

申请号：US11220529

申请日：2005-09-08

申请人： Kingo Ota ,  Shoichi Okuda ,  Hirofumi Abe

发明人： Kingo Ota ,  Shoichi Okuda ,  Hirofumi Abe

IPC分类号： H03B1/00

CPC分类号： H03K17/04206 ,  H03K17/0822

摘要： A semiconductor device for driving a load includes a first semiconductor switching element interposed between a power supply terminal and a load, a second semiconductor switching element interposed between the load and a ground terminal, a high-side driver, a low-side driver, and a voltage regulator. The voltage regulator reduces a voltage applied to a control terminal of the second switching element, when a voltage of a load terminal of the second switching element is lower than a predetermined voltage. Then, a voltage applied between the load terminal and the ground terminal of the second switching element increases, and accordingly a voltage applied between the power supply terminal and the load terminal of the first switching element decreases.

摘要翻译： 用于驱动负载的半导体装置包括插入在电源端子和负载之间的第一半导体开关元件，插入在负载和接地端子之间的第二半导体开关元件，高侧驱动器，低侧驱动器和 电压调节器。 当第二开关元件的负载端子的电压低于预定电压时，电压调节器减小施加到第二开关元件的控制端子的电压。 然后，施加在第二开关元件的负载端子和接地端子之间的电压增加，因此施加在第一开关元件的电源端子和负载端子之间的电压降低。

公开(公告)号：US06972973B2

公开(公告)日：2005-12-06

申请号：US10716560

申请日：2003-11-20

申请人： Hirofumi Abe ,  Hirokazu Itakura ,  Hiroyuki Ban ,  Shoichi Okuda ,  Kingo Ota

发明人： Hirofumi Abe ,  Hirokazu Itakura ,  Hiroyuki Ban ,  Shoichi Okuda ,  Kingo Ota

IPC分类号： H02M3/07 ,  H02M3/18 ,  G05F3/08

CPC分类号： H02M3/18 ,  H02M3/073

摘要： In a voltage booster, a voltage detection circuit detects a battery voltage as an input voltage. If the input voltage is lower than a threshold level, an oscillation circuit outputs a gate signal having a relatively high frequency to increase the driving performance of a driving circuit. If the input voltage is higher than the threshold level, the frequency of the gate signal is lowered so as to prevent the driving performance of the driving circuit from rising to an excessively high value. As a result, a predetermined boosted voltage can be obtained regardless of variations in input voltage without using a filter for eliminating noise.

摘要翻译： 在升压器中，电压检测电路检测电池电压作为输入电压。 如果输入电压低于阈值电平，则振荡电路输出具有较高频率的门信号，以提高驱动电路的驱动性能。 如果输入电压高于阈值电平，则门信号的频率降低，以防止驱动电路的驱动性能上升到过高的值。 结果，无需使用用于消除噪声的滤波器，就可以获得预定的升压电压而不管输入电压的变化。

公开(公告)号：US06614282B2

公开(公告)日：2003-09-02

申请号：US10270808

申请日：2002-10-14

申请人： Hirofumi Abe ,  Hiroshi Fujii ,  Sinichi Noda ,  Hideaki Ishihara

发明人： Hirofumi Abe ,  Hiroshi Fujii ,  Sinichi Noda ,  Hideaki Ishihara

IPC分类号： H03K508

CPC分类号： H03M1/1295

摘要： A comparator, having an offset of 0.1V, compares a terminal voltage Vin1 with a clamp voltage VCL (5.1V). When an overvoltage input exceeding the VCL is entered to an input terminal, the comparator turns on a transistor Q11. The current flows across an externally provided resistor R11, the input terminal, and the transistor Q11, and flows into an output terminal of an operational amplifier. With a voltage drop at the resistor R11, the terminal voltage Vin1 starts decreasing toward an output voltage Vc of the operational amplifier.

摘要翻译： 具有0.1V偏移的比较器将终端电压Vin1与钳位电压VCL（5.1V）进行比较。 当超过VCL的过压输入被输入到输入端时，比较器接通晶体管Q11。 电流流过外部提供的电阻器R11，输入端子和晶体管Q11，并流入运算放大器的输出端。 在电阻器R11处具有电压降，端子电压Vin1开始朝向运算放大器的输出电压Vc降低。

公开(公告)号：US5625218A

公开(公告)日：1997-04-29

申请号：US491543

申请日：1995-06-16

申请人： Hideya Yamadera ,  Takeshi Ohwaki ,  Yasunori Taga ,  Makio Iida ,  Makoto Ohkawa ,  Hirofumi Abe ,  Yoshihiko Isobe

发明人： Hideya Yamadera ,  Takeshi Ohwaki ,  Yasunori Taga ,  Makio Iida ,  Makoto Ohkawa ,  Hirofumi Abe ,  Yoshihiko Isobe

IPC分类号： H01L23/525 ,  H01L27/10 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002

摘要： A fuse fusible type semiconductor device capable of reducing energy required for fusing and a production method of the semiconductor device. In a semiconductor device equipped with a heat-fusible thin film resistor, the thin film resistor formed on a substrate 1 through an insulating film 2 is made of chromium, silicon and tungsten, and films 7 and 8 of a insulator including silicon laminated on the upper surface of the fusing surface, aluminum films 5 are disposed on both sides of the fusing surface and a barrier film 4. This semiconductor device is produced by a lamination step of sequentially forming a first insulating film 2, a thin film resistor 3, a barrier film 4 and an aluminum film 5 on a substrate 1 for reducing drastically fusing energy, an etching step of removing the barrier film 4 and the aluminum film 5 from the fusing region 31 of the thin film resistor 3, and an oxide film formation step of depositing the insulator including silicon films 7 and 8.

摘要翻译： 一种能够降低熔融所需的能量的熔断器熔断型半导体器件和半导体器件的制造方法。 在配备有热熔薄膜电阻器的半导体装置中，通过绝缘膜2形成在基板1上的薄膜电阻由铬，硅和钨制成，并且包含硅的绝缘体的膜7和8层压在 定影表面的上表面，铝膜5设置在定影表面的两侧和阻挡膜4上。该半导体器件通过层叠步骤制造，顺序形成第一绝缘膜2，薄膜电阻3， 阻挡膜4和铝膜5，用于降低显着熔化能的蚀刻步骤，从薄膜电阻器3的熔融区域31去除阻挡膜4和铝膜5的蚀刻步骤以及氧化膜形成步骤 沉积包括硅膜7和8的绝缘体。

公开(公告)号：US5623442A

公开(公告)日：1997-04-22

申请号：US379480

申请日：1995-01-31

申请人： Hiroshi Gotou ,  Mamoru Kondo ,  Hirofumi Abe

发明人： Hiroshi Gotou ,  Mamoru Kondo ,  Hirofumi Abe

IPC分类号： G11C11/00 ,  G11C11/404 ,  G11C14/00 ,  G11C16/04 ,  G11C16/10 ,  G11C17/00 ,  H01L21/30 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C11/005 ,  G11C11/404 ,  G11C14/00 ,  G11C16/10

摘要： An object of the present invention is to provide a DRAM of a special form, a non-volatile memory cell incorporating the DRAM, and a semiconductor device which incorporates a DRAM structure and a non-volatile memory cell and where data can be written and erased with high accuracy. The semiconductor memory device has a sub bit line BLs1 to which the main bit line BL1 is connected via a selector transistor Tr1, and non-volatile memory cells M1-Nn, i.e., memory transistors whose drain electrodes are connected to the sub bit line Bls1. An a-c pulse generator applies an a-c voltage to the control gates of the non-volatile memory cells M1-Nn. The DRAM cell is formed of a capacitor element formed of parasitic capacitance of the sub bit line BLs1 and the drain electrodes of the non-volatile memory cells connected to the bit line BLs1. An arbitrary non-volatile memory cell Mk is connected with the memory node N of a DRAM cell, thereby implementing a non-volatile memory cell or non-volatile memory device having DRAM functions. The DRAM cells may operate independently of the non-volatile memory cells. Data is temporarily stored in the DRAM cell and is then transferred to the non-volatile memory cell Mk, thereby writing and erasing data with high accuracy at higher speeds, and allowing miniaturization of a memory device.

摘要翻译： PCT No.PCT / JP94 / 00928 Sec。 371日期1995年1月31日 102（e）日期1995年1月31日PCT Filed 1994年6月8日PCT公布。 公开号WO95 / 02884 日期1995年1月26日本发明的目的是提供一种特殊形式的DRAM，并入DRAM的非易失性存储单元，以及结合DRAM结构和非易失性存储单元的半导体器件，其中数据 可以高精度写入和擦除。 半导体存储器件具有通过选择晶体管Tr1与主位线BL1连接的子位线BLs1，以及非易失性存储单元M1-Nn，即其漏电极连接到子位线B1s1的存储晶体管 。 a-c脉冲发生器将a-c电压施加到非易失性存储单元M1-Nn的控制栅极。 DRAM单元由与子位线BLs1的寄生电容和连接到位线BLs1的非易失性存储单元的漏极形成的电容器元件形成。 任意的非易失性存储单元Mk与DRAM单元的存储器节点N连接，从而实现具有DRAM功能的非易失性存储单元或非易失性存储器件。 DRAM单元可以独立于非易失性存储单元操作。 数据被暂时存储在DRAM单元中，然后传送到非易失性存储单元Mk，从而以更高的速度以高精度写入和擦除数据，并允许存储器件的小型化。

公开(公告)号：US20050238351A1

公开(公告)日：2005-10-27

申请号：US11113099

申请日：2005-04-25

申请人： Hirofumi Abe

发明人： Hirofumi Abe

IPC分类号： G03C5/00 ,  G03C1/76 ,  G03D3/08 ,  G03F7/26

CPC分类号： G03D3/08

摘要： A photographic light-sensitive material having a support having a thickness of from 160 to 225 μm is processed with an automatic developing apparatus, in which at least one of rollers of a developing part, a fixing part and a rinsing rack part of the automatic developing apparatus has a surface mainly containing a nonpolar polymer substance and having a center line surface roughness (Ra) of 20 μm or less. By using the automatic developing apparatus, dusts generated in the apparatus can be easily removed with a cleaning film.

摘要翻译： 具有160-225μm厚度的支撑体的照相感光材料用自动显影装置加工，其中自动显影装置中的显影部分，固定部分和清洗架部分中的至少一个辊子 装置具有主要包含非极性聚合物物质并且中心线表面粗糙度（Ra）为20μm以下的表面。 通过使用自动显影装置，可以用清洁膜容易地除去装置中产生的灰尘。

公开(公告)号：US20050201027A1

公开(公告)日：2005-09-15

申请号：US11079517

申请日：2005-03-15

申请人： Yoshinori Arashima ,  Hirofumi Abe ,  Shigeki Takahashi

发明人： Yoshinori Arashima ,  Hirofumi Abe ,  Shigeki Takahashi

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H02H9/00 ,  H03K17/08

CPC分类号： H03K17/0822 ,  H01L27/0266 ,  H01L29/0696 ,  H01L29/7816

摘要： The semiconductor output circuit of the invention has an insulated gate transistor including a first terminal, a second terminal and a gate terminal, a conductive state of the insulated gate transistor being controlled by a drive circuit connected to the gate terminal, a capacitive element and a first resistor connected in series between the second terminal and the gate terminal, and a second resistor connected between the gate terminal and the first terminal. The insulated gate transistor has a cell area formed on a semiconductor substrate, in which a plurality of unit cells each defining a unit transistor connected between the first and second terminals are laid out. The second resistor has such a resistance that all of the unit transistors defined by the unit cells are turned on uniformly when electrostatic discharge is applied to the first or second terminal.

摘要翻译： 本发明的半导体输出电路具有包括第一端子，第二端子和栅极端子的绝缘栅极晶体管，绝缘栅极晶体管的导通状态由连接到栅极端子的驱动电路，电容元件和 第一电阻器串联连接在第二端子和栅极端子之间，第二电阻器连接在栅极端子和第一端子之间。 绝缘栅极晶体管具有形成在半导体衬底上的单元区域，其中布置了连接在第一和第二端子之间的单元晶体管的多个单位单元。 第二电阻器具有这样的电阻，即当静电放电施加到第一或第二端子时，由单电池限定的所有单位晶体管均匀地导通。

公开(公告)号：US06903460B2

公开(公告)日：2005-06-07

申请号：US10689060

申请日：2003-10-21

申请人： Yutaka Fukuda ,  Hirofumi Abe ,  Yoshinori Arashima ,  Shigeki Takahashi

发明人： Yutaka Fukuda ,  Hirofumi Abe ,  Yoshinori Arashima ,  Shigeki Takahashi

IPC分类号： H01L21/3205 ,  H01L23/482 ,  H01L23/52 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L23/48

CPC分类号： H01L29/7816 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/41758 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor equipment includes a semiconductor substrate, a plurality of transistors having a source cell and a drain cell disposed alternately on the substrate, and upper and lower layer wirings for electrically connecting the source cells and the drain cells. The lower layer wiring includes a first source wiring for connecting the neighboring source cells and a first drain wiring for connecting the neighboring drain cells. The upper layer wiring includes a second source wiring for connecting to the first source wiring and a second drain wiring for connecting to the first drain wiring. A width of the second source wiring is wider than that of the first source wiring, and a width of the second drain wiring is wider than that of the first drain wiring. The second source wiring and the second drain wiring are disposed alternately.

摘要翻译： 半导体设备包括半导体衬底，具有交替放置在衬底上的源极单元和漏极单元的多个晶体管，以及用于电连接源极单元和漏极单元的上部和下部布线。 下层布线包括用于连接相邻源极单元的第一源极布线和用于连接相邻漏极单元的第一漏极布线。 上层布线包括用于连接到第一源极布线的第二源极布线和用于连接到第一漏极布线的第二漏极布线。 第二源极布线的宽度比第一源极布线的宽度宽，并且第二漏极布线的宽度比第一漏极布线的宽度宽。 第二源极配线和第二漏极配线交替配置。