公开(公告)号：US10325056B1

公开(公告)日：2019-06-18

申请号：US15179087

申请日：2016-06-10

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu

IPC: G06F17/50

Abstract: A system, methods, and a computer program product for estimating a yield and creating corners of a circuit design with the aid of a failure boundary classification. The system, methods and computer program product provide for determining, based on how many sampling factors have failures, whether data samples are sufficient as input to scaled-sigma sampling. If the data samples are insufficient, the failure boundary classification is usable to determine whether the yield is high enough to meet a yield target. A design corner can be located by applying a binary search to results of scaled-sigma sampling. The failure boundary classification can aid in setting up the search.

公开(公告)号：US10275555B1

公开(公告)日：2019-04-30

申请号：US15280839

申请日：2016-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Shikha Sharma ,  Hongzhou Liu

IPC: G06F9/455 ,  G06F17/50

Abstract: Method for estimating a yield of a post-layout circuit design is provided. In one aspect, a method includes obtaining a first pre-layout parameter and a second pre-layout parameter from pre-layout simulation samples of a circuit. The method also modeling a prior distribution of a first post-layout parameter and a second post-layout parameter based on the first pre-layout parameter, the second pre-layout parameter, a first hyper-parameter, and second hyper-parameter. The method further includes calculating the first hyper-parameter and the second hyper-parameter using a cross-validation, obtaining the first post-layout parameter and the second post-layout parameter based on the first hyper-parameter and the second hyper-parameter and estimating the yield of the circuit design using a non-normal distribution parameterized by the obtained first post-layout parameter and second post-layout parameter.

公开(公告)号：US09836564B1

公开(公告)日：2017-12-05

申请号：US14683021

申请日：2015-04-09

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5045

Abstract: A system, method, and computer program product for reducing the number of Monte Carlo simulation samples required to determine if a design meets design specifications. The worst sample for each specification acts as a design corner to substitute for a full design verification. Embodiments determine the maximum number of samples needed, perform an initial performance modeling using an initial set of samples, and estimate the failure probability of each of the remaining samples based on the performance model. Embodiments then simulate remaining samples with a computer-operated Monte Carlo circuit simulation tool in decreasing design specification model accuracy order, wherein the sample predicted most likely to fail each specification is simulated first. Re-use of simulation results progressively improves models. Probability based stop criteria end the simulation early when the worst samples have been confidently found. A potential ten-fold reduction in overall specification verification time may result.

公开(公告)号：US11416660B1

公开(公告)日：2022-08-16

申请号：US17138833

申请日：2020-12-30

Applicant: Cadence Design Systems, Inc.

Inventor： Preeti Kapoor ,  Hui Xu ,  Hongzhou Liu ,  Sravasti G. Nair

IPC: G06F30/31 ,  G06F30/3308 ,  G06N3/12 ,  G06F30/392

Abstract: Disclosed is an improved approach to implement analog or mixed-signal designs. A method, system, and computer program product are provided to fully automate the analog placement step using a virtual grouping methodology which considers variable components and uses a genetic placement algorithm to find the best placement solution which fully respects the analog constraints defined by a user or auto identified by a tool.

公开(公告)号：US10909293B1

公开(公告)日：2021-02-02

申请号：US16655570

申请日：2019-10-17

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu ,  Richard J. O'Donovan ,  Michael Tian

IPC: G06F30/367 ,  G06F119/18 ,  G06F111/10

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

公开(公告)号：US10776548B1

公开(公告)日：2020-09-15

申请号：US15471871

申请日：2017-03-28

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Wangyang Zhang

IPC: G06F30/367 ,  G06F111/10

Abstract: A method for determining the tail performance of an integrated circuit is described. The method includes simulating the integrated circuit over samples to obtain values for circuit specifications and sorting the circuit specifications based on an expected number of samples. The method also includes arranging a sequence of samples from the universe according to a sequence in the group of circuit specifications, simulating the integrated circuit with one of the sequence of samples to obtain at least one circuit specification, removing the at least one circuit specification from the group when it satisfies the stop criterion, and modifying a model for a second circuit specification based on the at least one circuit specification. The computer-implemented method also includes reordering the group of circuit specifications based on the model and determining an integrated circuit performance based on a simulation result for the at least one circuit specification.

公开(公告)号：US10528644B1

公开(公告)日：2020-01-07

申请号：US15638947

申请日：2017-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu

IPC: G06F17/50 ,  G06F17/18

Abstract: A method for visualizing a performance distribution of an integrated circuit (IC) design is provided. The method includes determining a yield limit based on a group of Monte Carlo simulations of the IC design, and a functional yield, and selecting an initial yield based on an initial specification value from the group of Monte Carlo simulations. The method also includes selecting additional yield values based on additional specification values and on the group of Monte Carlo simulations of the IC design, wherein the low yield values are estimated using Kernel Density Estimation, and the high yield values are estimated using repeated binary search. The cumulative distribution function and probability density function for a performance of the IC design are estimated based on the additional yield values and the additional specification values. Also, the method includes obtaining a quantile representation for the performance of the IC design from the cumulative distribution function.

公开(公告)号：US10289764B1

公开(公告)日：2019-05-14

申请号：US15247675

申请日：2016-08-25

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Wangyang Zhang

IPC: G06F17/50 ,  G06F12/0875

Abstract: Methods and systems are provided. In one aspect, a method for parallel extraction of worst case corners of a number of electronic design automation (EDA) simulations includes generating multiple initial EDA simulation results for a number of specifications of an integrated circuit based on a first algorithm. For each specification, a respective first set of input samples is generated based on a second algorithm using generated multiple initial simulation results. Using a third algorithm, two or more of the respective first set of input samples are merged based on a criterion to generate a respective second set of input samples. For each specification, a first set of simulation results is generated using the respective second set of input samples. The worst case corners for the specifications are determined by applying in parallel local optimization to the first set of simulation results.

公开(公告)号：US10114916B1

公开(公告)日：2018-10-30

申请号：US15198864

申请日：2016-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Daniel da Fonseca Munford Argollo ,  Ankur Duggal ,  Iain G. Farquharson ,  Hongzhou Liu

IPC: G06F17/50 ,  G06F17/30 ,  G06T11/20 ,  G06F3/0489 ,  G06F11/32

Abstract: An improved approach is provided to provide fast access to waveform visualizations for electronic designs. Data reduction is performed on the waveform data, where the quantity of the waveform data is reduced in an intelligent manner, such that the reduced waveform data still retains sufficient data fidelity for accurate data analysis and waveform visualization. The reduced data can then be displayed in an accelerated manner. From the display of the reduced data, this allows the user to select only the specific one or more waveforms for which the user seeks viewing of the full waveform data.

公开(公告)号：US09524365B1

公开(公告)日：2016-12-20

申请号：US14581958

申请日：2014-12-23

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Wangyang Zhang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009

Abstract: A system, method, and computer program product for automatically reducing the number of Monte Carlo simulation samples required to determine if a design yield is above or below a given yield target with a given confidence. Embodiments perform an initial Monte Carlo based performance modeling using an initial set of statistical samples, and estimate the failure probability of each of the remaining statistical samples based on the performance model. Embodiments then simulate each of the remaining statistical samples with a computer-operated Monte Carlo circuit simulation tool in decreasing failure probability order, wherein the sample most likely to fail is simulated first. Progressive comparisons of the simulated yield against a yield target eventually verify the yield at a required confidence level, halting the simulation and triggering tangible output of the comparison results. A potential ten-fold decrease in overall yield verification time without loss of accuracy may result.

Abstract translation: 一种用于自动减少蒙特卡罗模拟样本数量的系统，方法和计算机程序产品，用于确定设计产量是否高于或低于给定屈服目标，并具有给定的置信度。 实施例使用初始的统计样本集执行初始的基于蒙特卡罗的性能建模，并且基于性能模型来估计每个剩余统计样本的故障概率。 然后，实施例使用计算机操作的蒙特卡洛电路仿真工具以降低的故障概率顺序模拟每个剩余的统计样本，其中首先模拟最可能失败的样本。 模拟产量与产量目标的进一步比较最终在所需的置信水平上验证产量，停止模拟并触发比较结果的有形输出。 可能导致整体产量验证时间的潜在十倍下降而不损失精度。