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Patent Agency Ranking
公开(公告)号：US09819520B1
公开(公告)日：2017-11-14
申请号：US15380932
申请日：2016-12-15
Applicant: Cadence Design Systems, Inc.
Inventor： Scott David Huss
CPC classification number: H04L25/03057 , H04L25/03343
Abstract: A circuit and method for controlling a pre-cursor coefficient in an equalizer of a transmitter device. An input signal from the transmitter is converted into a data signal that includes data symbols transmitted in successive unit intervals. An error signal is formed by comparing the input signal to a threshold value. A determination is made whether to adjust the pre-cursor coefficient, by correlating a sample of the error signal with samples of the data signal from one unit interval earlier and two unit intervals earlier.
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公开(公告)号：US11228416B1
公开(公告)日：2022-01-18
申请号：US16944036
申请日：2020-07-30
Applicant: Cadence Design Systems, Inc.
Inventor： Scott David Huss , Loren B. Reiss , Christopher George Moscone , James Dennis Vandersand, Jr.
Abstract: Various embodiments provide for calibrating one or more clock signals for a serializer, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, for a serializer operating based on a plurality of clock signals, some embodiments provide for calibration of one or more of the plurality of clock signals by adjusting a duty cycle of one or more clock signals, a delay of one or more clock signals, or both.
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公开(公告)号：US11165554B1
公开(公告)日：2021-11-02
申请号：US17081790
申请日：2020-10-27
Applicant: Cadence Design Systems, Inc.
Inventor： Scott David Huss , Jeffrey Andrew Shafer
Abstract: Various embodiments provide for testing a transmitter using a phase-lock loop, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer using a sample clock signal generated by an M/N phase-lock loop (PLL); and using a pattern checker to error check the sampled data to determine whether the data transmission test passes.
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公开(公告)号：US11165553B1
公开(公告)日：2021-11-02
申请号：US17018529
申请日：2020-09-11
Applicant: Cadence Design Systems, Inc.
Inventor： Loren B. Reiss , Scott David Huss , Christopher George Moscone
Abstract: A phase interpolator of a physical layer (PHY) device comprise a phase interpolator to generate a set of asynchronous sampler clocks. A sampler of the PHY device samples a calibration data pattern using a first sampler clock from the set of asynchronous sampler clocks. A calibration control component of the PHY device detects a misalignment of a phase relationship among the set of asynchronous sampler clocks based on the sampled data. In response to detecting the misalignment, the calibration control component calibrates the first sampler clock using a second sampler clock and a third sampler clock.
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公开(公告)号：US10355889B1
公开(公告)日：2019-07-16
申请号：US15376037
申请日：2016-12-12
Applicant: Cadence Design Systems, Inc.
Inventor： Scott David Huss , Guillaume Fortin
Abstract: Systems and methods disclosed herein provide for adaptively applying pattern filters so that the edges are discarded only when the DFE feedback has adapted to levels that can corrupt the timing recovery. Embodiments of the systems and methods provide for a phase detector that selectively suppresses timing information based on the logic level states of the Qp and Qm data samples associated with the received signal.
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