公开(公告)号：US07730284B2

公开(公告)日：2010-06-01

申请号：US10549368

申请日：2004-03-17

申请人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Antonio Alba Pinto

发明人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Antonio Alba Pinto

IPC分类号： G06F9/30

CPC分类号： G06F8/445 ,  G06F9/30141 ,  G06F9/3826 ,  G06F9/3859 ,  G06F9/3865 ,  G06F9/3869

摘要： An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to selectively disable storing of the results in the register file under control of the instructions.

摘要翻译： 指令处理装置具有管线级，其具有用于从指令执行命令的功能单元。 第一寄存器单元耦合到功能单元，用于当命令已经到达第一个流水线级时存储命令的执行结果，并且用于将旁路操作数数据提供给功能单元。 寄存器文件耦合到功能单元，用于当命令已经到达第一个流水线级的第一个流水线级的下游，并且将操作数数据提供给功能单元时存储结果。 耦合禁止电路以在指令的控制下选择性地禁止将结果存储在寄存器文件中。

公开(公告)号：US20080133880A1

公开(公告)日：2008-06-05

申请号：US10561454

申请日：2004-06-22

申请人： Carlos Antonio Alba Pinto ,  Balakrishnan Srinivasan ,  Ramanathan Sethuraman

发明人： Carlos Antonio Alba Pinto ,  Balakrishnan Srinivasan ,  Ramanathan Sethuraman

IPC分类号： G06F15/76 ,  G06F9/30

CPC分类号： G06F9/3826 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/152

摘要： The data processing device has a plurality of functional units and issues instructions in successive instruction cycles. Instructions of a first type are each intended for one functional unit at a time. An instruction of a second type causes a combination of functional units to respond in the same instruction execution cycle, a result from one functional unit being used by another as part of the execution of the same instruction. Preferably, the device supports alternative operation at a number of different instruction cycle rates, dependent on whether an executed program segment contains instructions of the second type. The fastest instruction cycle rate does not allow execution of the instruction of the second type, because operation by different functional units does not fit within the instruction execution cycle. When possible, the device saves power by switching to a slower clock rate, in which case instructions of the second type are executed to save additional power, by reducing the number of instructions that have to be issued.

摘要翻译： 数据处理装置具有多个功能单元并在连续的指令周期中发出指令。 第一种类型的说明每次都用于一个功能单元。 第二类型的指令使得功能单元的组合在相同的指令执行周期中作出响应，这是由另一个功能单元作为执行相同指令的一部分使用的结果。 优选地，该设备支持多个不同指令周期速率的替代操作，取决于所执行的程序段是否包含第二类型的指令。 最快的指令周期速率不允许执行第二种指令，因为不同功能单元的操作不符合指令执行周期。 如果可能，设备通过切换到较慢的时钟速率来节省功率，在这种情况下，通过减少必须发出的指令数量来执行第二种类型的指令以节省额外的功率。

公开(公告)号：US07861062B2

公开(公告)日：2010-12-28

申请号：US10561454

申请日：2004-06-22

申请人： Carlos Antonio Alba Pinto ,  Balakrishnan Srinivasan ,  Ramanathan Sethuraman

发明人： Carlos Antonio Alba Pinto ,  Balakrishnan Srinivasan ,  Ramanathan Sethuraman

IPC分类号： G06F9/30

CPC分类号： G06F9/3826 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/152

摘要： The data processing device has a plurality of functional units and issues instructions in successive instruction cycles. Instructions of a first type are each intended for one functional unit at a time. An instruction of a second type causes a combination of functional units to respond in the same instruction execution cycle, a result from one functional unit being used by another as part of the execution of the same instruction. Preferably, the device supports alternative operation at a number of different instruction cycle rates, dependent on whether an executed program segment contains instructions of the second type. The fastest instruction cycle rate does not allow execution of the instruction of the second type, because operation by different functional units does not fit within the instruction execution cycle. When possible, the device saves power by switching to a slower clock rate, in which case instructions of the second type are executed to save additional power, by reducing the number of instructions that have to be issued.

摘要翻译： 数据处理装置具有多个功能单元并在连续的指令周期中发出指令。 第一种类型的说明每次都用于一个功能单元。 第二类型的指令使得功能单元的组合在相同的指令执行周期中作出响应，这是由另一个功能单元作为执行相同指令的一部分使用的结果。 优选地，该设备支持多个不同指令周期速率的替代操作，取决于所执行的程序段是否包含第二类型的指令。 最快的指令周期速率不允许执行第二种指令，因为不同功能单元的操作不符合指令执行周期。 如果可能，设备通过切换到较慢的时钟速率来节省功率，在这种情况下，通过减少必须发出的指令数量来执行第二种类型的指令以节省额外的功率。

公开(公告)号：US20180165200A1

公开(公告)日：2018-06-14

申请号：US15374042

申请日：2016-12-09

申请人： Ramanathan Sethuraman

发明人： Ramanathan Sethuraman

IPC分类号： G06F12/0842 ,  G06F12/0875

CPC分类号： G06F9/3802 ,  G06F9/381 ,  G06F11/30

摘要： In one embodiment, a processor includes: a plurality of cores; a plurality of caches associated with the plurality of cores; a dynamic profiler to identify a plurality of instructions having an activity level greater than a threshold level, the dynamic profiler a shared resource of the processor; and a controller to dynamically enable one or more of the plurality of cores to access the dynamic profiler, where the controller is to enable the dynamic profiler to provide hint information regarding the plurality of instructions to a first core of the plurality of cores. Other embodiments are described and claimed.

公开(公告)号：US20150350666A1

公开(公告)日：2015-12-03

申请号：US14287967

申请日：2014-05-27

申请人： Vladimir Kovacevic ,  Zdravko Pantic ,  Aleksandar Beric ,  Ramanathan Sethuraman ,  Jean-Pierre Giacalone ,  Anton Igorevich Veselov ,  Marat Ravilevich Gilmutdinov

发明人： Vladimir Kovacevic ,  Zdravko Pantic ,  Aleksandar Beric ,  Ramanathan Sethuraman ,  Jean-Pierre Giacalone ,  Anton Igorevich Veselov ,  Marat Ravilevich Gilmutdinov

IPC分类号： H04N19/503

CPC分类号： H04N19/503 ,  H04N19/102 ,  H04N19/137 ,  H04N19/14 ,  H04N19/176 ,  H04N19/587 ,  H04N19/85

摘要： Methods, apparatus, systems and articles of manufacture to perform block-based static region detection for video processing are disclosed. Disclosed example video processing methods include segmenting pixels in a first frame of a video sequence into a first plurality of pixel blocks. Such example methods can also include processing the first plurality of pixel blocks and a second plurality of pixel blocks corresponding to a prior second frame of the video sequence to create, based on a first criterion, a map identifying one or more static pixel blocks in the first plurality of pixel blocks. Such example methods can further include identifying, based on the map, a static region in the first frame of the video sequence.

摘要翻译： 公开了用于执行视频处理的基于块的静态区域检测的方法，装置，系统和制品。 公开的示例视频处理方法包括将视频序列的第一帧中的像素分割为第一多个像素块。 这样的示例性方法还可以包括处理第一多个像素块和与视频序列的先前第二帧相对应的第二多个像素块，以基于第一准则创建标识一个或多个静态像素块中的一个或多个静态像素块的映射 第一多个像素块。 这样的示例方法还可以包括基于该图来识别视频序列的第一帧中的静态区域。

公开(公告)号：US20090219446A1

公开(公告)日：2009-09-03

申请号：US12092129

申请日：2006-10-27

申请人： Aleksandar Beric ,  Ramanathan Sethuraman

发明人： Aleksandar Beric ,  Ramanathan Sethuraman

IPC分类号： H04N9/64

CPC分类号： H04N19/433 ,  H04N19/43 ,  H04N19/61

摘要： A data processing system is provided for processing video data on a window basis. At least one memory unit (L1) is provided for fetching and storing video data from an image memory (IM) according to a first window (R) in a first scanning order. At least one second memory unit (L0) is provided for fetching and storing video data from the first memory unit (L1) according to a second window in a second scanning order (SO). Furthermore, at least one processing unit (PU) is provided for performing video processing on the video data of the second window as stored in the at least one second memory unit (L0) based on the second scanning order (SO). The second scanning order (SO) is a meandering scanning order being orthogonal to the first scanning order (SO1).

摘要翻译： 提供了一种用于在窗口基础上处理视频数据的数据处理系统。 提供至少一个存储单元（L1），用于以第一扫描顺序从根据第一窗口（R）的图像存储器（IM）中提取和存储视频数据。 提供至少一个第二存储器单元（L0），用于以第二扫描顺序（SO）从根据第二窗口的第一存储器单元（L1）提取和存储视频数据。 此外，提供至少一个处理单元（PU），用于基于第二扫描顺序（SO）对存储在至少一个第二存储器单元（L0）中的第二窗口的视频数据执行视频处理。 第二扫描顺序（SO）是与第一扫描顺序（SO1）正交的曲折扫描顺序。

公开(公告)号：US20090135192A1

公开(公告)日：2009-05-28

申请号：US12299671

申请日：2007-05-07

申请人： Carlos Antonio Alba Pinto ,  Ramanathan Sethuraman

发明人： Carlos Antonio Alba Pinto ,  Ramanathan Sethuraman

IPC分类号： G09G5/39

CPC分类号： G06T1/60

摘要： A programmable data processing circuit has a memory for storing pixel values, or more generally data values as a function of position in a signal. The programmable data processing circuit supports instructions that include an indication of a selected parameter value set that indicates how a plurality of data values must be arranged for parallel output from a memory. Instructions that indicate different parameter value sets can be executed intermixed with one another. The programmable data processing circuit responds to instructions of this type by retrieving the selected parameter value sets from a parameter storage circuit (246), and controlling a switching circuit (22) between a memory port (21) of a memory circuit (20) and a data port (26) at least partly dependent on the selected parameter value set.

摘要翻译： 可编程数据处理电路具有用于存储像素值的存储器，或更一般地，作为信号中的位置的函数的数据值。 可编程数据处理电路支持指令，其包括指示如何为存储器并行输出多个数据值的选定参数值集合的指示。 指示不同参数值集的指令可以执行相互混合。 可编程数据处理电路通过从参数存储电路（246）检索所选择的参数值集合以及控制存储器电路（20）的存储器端口（21）和存储器电路（20）的存储器端口（21）之间的切换电路（22）和 至少部分地依赖于所选择的参数值集合的数据端口（26）。

公开(公告)号：US08339405B2

公开(公告)日：2012-12-25

申请号：US12299671

申请日：2007-05-07

申请人： Carlos Antonio Alba Pinto ,  Ramanathan Sethuraman

发明人： Carlos Antonio Alba Pinto ,  Ramanathan Sethuraman

IPC分类号： G09G5/39 ,  G06F13/18 ,  G06F13/00

CPC分类号： G06T1/60

摘要： A programmable data processing circuit has a memory for storing pixel values, or more generally data values as a function of position in a signal. The programmable data processing circuit supports instructions that include an indication of a selected parameter value set that indicates how a plurality of data values must be arranged for parallel output from a memory. Instructions that indicate different parameter value sets can be executed intermixed with one another. The programmable data processing circuit responds to instructions of this type by retrieving the selected parameter value sets from a parameter storage circuit (246), and controlling a switching circuit (22) between a memory port (21) of a memory circuit (20) and a data port (26) at least partly dependent on the selected parameter value set.

摘要翻译： 可编程数据处理电路具有用于存储像素值的存储器，或更一般地，作为信号中的位置的函数的数据值。 可编程数据处理电路支持指令，其包括指示如何为存储器并行输出多个数据值的选定参数值集合的指示。 指示不同参数值集的指令可以执行相互混合。 可编程数据处理电路通过从参数存储电路（246）检索所选择的参数值集合以及控制存储器电路（20）的存储器端口（21）和存储器电路（20）的存储器端口（21）之间的切换电路（22）和 至少部分地依赖于所选择的参数值集合的数据端口（26）。

公开(公告)号：US07797493B2

公开(公告)日：2010-09-14

申请号：US11815981

申请日：2006-02-13

申请人： Harm Johannes Antonius Maria Peters ,  Ramanathan Sethuraman ,  Gerard Veldman ,  Patrick Peter Elizabeth Meuwissen

发明人： Harm Johannes Antonius Maria Peters ,  Ramanathan Sethuraman ,  Gerard Veldman ,  Patrick Peter Elizabeth Meuwissen

IPC分类号： G06F13/28

CPC分类号： H04N19/433 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/6022 ,  G06T7/20 ,  G06T2200/28 ,  G09G5/395 ,  G09G2320/0261 ,  G09G2360/121 ,  H04N19/436

摘要： The present invention relates to a data processing device (10) comprising a processing unit (12) and a memory unit (14), and to a method for controlling operation of a memory unit (14) of a data processing device. The memory unit (14) comprises a main memory (16), a low- level cache memory (20.2), which is directly connected to the processing unit (12) and adapted to hold all pixels of a currently active sliding search area for reading access by the processing unit (12), a high-level cache memory (18), which is connected between the low-level cache memory and the frame memory, and a first pre-fetch buffer (20.1), which is connected between the high-level cache memory and the low- level cache memory and which is adapted to hold one search-area column or one search-area line of pixel blocks, depending on the scan direction and scan order followed by the processing unit. Reading and fetching functionalities are decoupled in the memory unit (14). The fetching functionality is concentrated on the higher cache level, while the reading functionality is concentrated on the lower cache level. This way concurrent reading and fetching can be achieved, thus enhancing the performance of a data processing device.

摘要翻译： 本发明涉及包括处理单元（12）和存储单元（14）的数据处理设备（10），以及用于控制数据处理设备的存储单元（14）的操作的方法。 存储单元（14）包括主存储器（16），低级高速缓存存储器（20.2），其直接连接到处理单元（12）并且适于保持当前活动的滑动搜索区域的所有像素用于读取 处理单元（12）的访问，连接在低级缓存存储器和帧存储器之间的高级缓存存储器（18）和第一预取缓冲器（20.1），其连接在 高级缓存存储器和低级高速缓存存储器，并且其适于保持像素块的一个搜索区域列或一个搜索区域行，这取决于处理单元后面的扫描方向和扫描顺序。 读取和取出功能在存储器单元（14）中解耦。 获取功能集中在较高的缓存级别，而读取功能集中在较低的缓存级别。 这样可以实现并行读取和取出，从而提高数据处理设备的性能。

公开(公告)号：US20070019874A1

公开(公告)日：2007-01-25

申请号：US10570546

申请日：2004-08-26

申请人： Ramanathan Sethuraman ,  Fabian Ernst

发明人： Ramanathan Sethuraman ,  Fabian Ernst

IPC分类号： G06K9/36

CPC分类号： H04N19/428 ,  H04N19/39 ,  H04N21/2343 ,  H04N21/2662 ,  H04N21/4402 ,  H04N21/4621

摘要： The invention relates to content signal processing and in particular to processing of a video content signal. An apparatus (100) for content signal processing comprises a scalable encoder (101) for encoding a content signal to generate scalable encoded data comprising data associated with a plurality of compression rates. A compression processor (105) determines compression factor indicators indicating data associated with the plurality of compression rates. Thus, the compression factor indicators indicate which data of the scalable encoded data corresponds to the different compression rates. Combined data comprising the scalable encoded data and the compression factor indicators are stored in a frame memory (105). An application having a given compression factor requirement may use the compression factor indicators to access the scalable encoded data of the frame memory (105) which is required for processing. A plurality of applications may access the same frame memory (105) thereby allowing for scalable encoded data which can be used with a plurality of applications having different compression factor requirements.

摘要翻译： 本发明涉及内容信号处理，特别涉及视频内容信号的处理。 用于内容信号处理的装置（100）包括可缩放编码器（101），用于对内容信号进行编码以产生包括与多个压缩率相关联的数据的可分级编码数据。 压缩处理器（105）确定指示与多个压缩率相关联的数据的压缩因子指示符。 因此，压缩因子指示符指示可缩放编码数据的哪个数据对应于不同的压缩率。 包括可缩放编码数据和压缩因子指示符的组合数据被存储在帧存储器（105）中。 具有给定压缩因子要求的应用可以使用压缩因子指示符来访问处理所需的帧存储器（105）的可缩放编码数据。 多个应用可以访问相同的帧存储器（105），从而允许可以与具有不同压缩因子要求的多个应用使用的可缩放编码数据。