公开(公告)号：US5956333A

公开(公告)日：1999-09-21

申请号：US781631

申请日：1997-01-10

Applicant: Changming Zhou ,  Guoliang Shou ,  Kenzo Urabe ,  Tetsuhiko Miyatani

Inventor： Changming Zhou ,  Guoliang Shou ,  Kenzo Urabe ,  Tetsuhiko Miyatani

IPC: H03H17/00 ,  H04B1/7107 ,  H04J13/00 ,  H04K1/00

CPC classification number: H04B1/71075

Abstract: A multi-user demodulator eliminates synchronization problems without interference cancellation. A threshold process is applied to a despread signal to extract each user's signal. The extracted signals are respread, and those respread signals other than a specifier user's signal are subtracted from the received signal to ideally extract the specific user's signal.

Abstract translation: 多用户解调器消除了无干扰消除的同步问题。 对解扩信号应用阈值处理以提取每个用户的信号。 提取的信号被重新发送，并且从接收到的信号中减去除指定者用户信号之外的那些再现信号，以理想地提取特定用户的信号。

公开(公告)号：US5930157A

公开(公告)日：1999-07-27

申请号：US895272

申请日：1997-07-16

Applicant: Ichiro Matsumoto ,  Changming Zhou ,  Guoliang Shou

Inventor： Ichiro Matsumoto ,  Changming Zhou ,  Guoliang Shou

IPC: G06F17/10 ,  G06F17/15 ,  G06J1/00 ,  G06F7/12

CPC classification number: G06J1/00

Abstract: The autocorrelation coefficient operator 60 carries out an integration operation to determine the autocorrelation coefficient for audio signal processing or other types of signal processing at high speed with low power consumption. The input signal S is digitized in the A/D converter 30 to the digital signal SP and supplied to a delay unit 40, which delays and holds the digital signal SP sequentially. A sample holder 45 also samples and holds the analog signal S in synchronization with the delay unit 40. When the number of sampled values held by the sample holder 45 reaches a predetermined value, the sample holder 45 outputs the sampled values at the same time in accordance with a sampling clock signal CK which is supplied by a clock signal generator 35. Delayed values held in the delay unit 40 are shifted and output sequentially in accordance with a shift clock signal SCK, the frequency of which is higher than that of the sampling clock signal CK. A weighted addition circuit 50 integrates these sampled values and the delayed values to calculate the autocorrelation coefficient R.

Abstract translation: 自相关系数运算器60执行积分运算，以低功耗确定音频信号处理的自相关系数或其他类型的信号处理。 输入信号S在A / D转换器30中数字化为数字信号SP，并提供给延迟单元40，延迟单元40依次延迟和保持数字信号SP。 样本保持器45还与延迟单元40同步地采样并保持模拟信号S.当采样保持器45保持的采样值的数量达到预定值时，样本保持器45同时输出采样值 根据由时钟信号发生器35提供的采样时钟信号CK。保持在延迟单元40中的延迟值根据频率高于采样的移位时钟信号SCK被顺序移位和输出 时钟信号CK。 加权加法电路50对这些采样值和延迟值进行积分，以计算自相关系数R.

公开(公告)号：US5815812A

公开(公告)日：1998-09-29

申请号：US760257

申请日：1996-12-05

Applicant: Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

Inventor： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

IPC: H04J13/00 ,  H04B1/7093 ,  H04W36/18 ,  H04W36/36 ,  H04Q7/32

CPC classification number: H04B1/7093 ,  H04W36/18

Abstract: The present invention provides a system for soft handoff, which processes in high speed. A system according to the present invention substantially realizes a multiplication by a circuit for classifying received signals from a plurality of cell site stations once held in an analog sampling and holding circuit into two groups, multiplication and accumulation, by a small circuit of low electric power consumption.

Abstract translation: 本发明提供了一种用于软切换的系统，其高速处理。 根据本发明的系统基本上实现了一种电路的乘法，该电路用于将一次保持在模拟采样和保持电路中的多个小区站点的接收信号分类成两组，通过低功率的小电路进行乘法和累加 消费。

公开(公告)号：US5815021A

公开(公告)日：1998-09-29

申请号：US686761

申请日：1996-07-26

Applicant: Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

Inventor： Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

IPC: G06G7/14 ,  G06J1/00 ,  G06G7/16

CPC classification number: G06J1/00 ,  G06G7/14

Abstract: The present invention provides a weighted addition circuit for sampling, holding and performing weighted addition by a circuit smaller than a conventional one. In the weighted addition circuit of to the present invention, a capacitive coupling is connected to a plurality of switches which are further connected only to an input voltage. A voltage is held and a weight is added in the capacitive coupling.

Abstract translation: 本发明提供一种加权加法电路，用于通过比传统电路小的电路进行采样，保持和执行加权相加。 在本发明的加权加法电路中，电容耦合连接到多个开关，该开关进一步仅与输入电压相连。 在电容耦合中保持电压并加上重量。

公开(公告)号：US06625205B1

公开(公告)日：2003-09-23

申请号：US09332198

申请日：1999-06-14

Applicant: Changming Zhou ,  Kunihiko Suzuki

Inventor： Changming Zhou ,  Kunihiko Suzuki

IPC: H04L2706

CPC classification number: H04B1/7093 ,  H04B1/708 ,  H04B2201/7071

Abstract: A matched filter having a set of registers to successively store a digital voltage. The matched filter includes a cumulative shift register, a number of exclusive-or circuits, and an analog adder. The cumulative shift register has a number of stages in which each stage has one bit corresponding to the shift register. The exclusive-or circuits each perform an exclusive-or function on each bit of the digital data and the one bit coefficient while the analog adder sums outputs from the exclusive-or circuits.

Abstract translation: 具有一组寄存器以连续存储数字电压的匹配滤波器。 匹配滤波器包括累积移位寄存器，多个异或电路和模拟加法器。 累积移位寄存器具有多个阶段，其中每个级具有对应于移位寄存器的一位。 在模拟加法器对来自异或电路的输出进行求和时，异或电路各自对数字数据的每一位和一位系数进行排他或功能。

公开(公告)号：US06340942B1

公开(公告)日：2002-01-22

申请号：US09413475

申请日：1999-10-06

Applicant: Changming Zhou ,  Kunihiko Suzuki ,  Takashi Tomatsu ,  Masataka Fukui

Inventor： Changming Zhou ,  Kunihiko Suzuki ,  Takashi Tomatsu ,  Masataka Fukui

IPC: H03M134

CPC classification number: H03M1/42

Abstract: An analog to digital converter comprises a differential input portion that receives an input voltage and a reference voltage and has a first and second output terminals, a positive feedback portion connected to said first and second output terminals, a buffer if CMOSFETs connected at its input to the first output terminal, a second buffer connected at its input to the second output terminal, and a comparison circuit including a first switching portion connected between the first and second output terminals for connecting and disconnecting the first and second output terminals in response to a comparison clock signal. The comparison circuit is connected at its output to the first or second buffer. The input voltage and the reference voltage are compared when said switching portion changes from the connecting condition to the disconnecting condition in response to the comparison clock signal.

Abstract translation: 模数转换器包括差分输入部分，其接收输入电压和参考电压，并且具有第一和第二输出端子，连接到所述第一和第二输出端子的正反馈部分，如果CMOSFET在其输入端连接到 第一输出端子，在其输入端连接到第二输出端子的第二缓冲器，以及比较电路，包括连接在第一和第二输出端子之间的第一开关部分，用于响应于比较来连接和断开第一和第二输出端子 时钟信号。 比较电路在其输出端连接到第一或第二缓冲器。 当所述切换部分响应于比较时钟信号而从连接状态变为断开状态时，比较输入电压和参考电压。

公开(公告)号：US06263012B1

公开(公告)日：2001-07-17

申请号：US09174910

申请日：1998-10-19

Applicant: Changming Zhou ,  Xuping Zhou ,  Guoliang Shou ,  Mamoru Sawahashi ,  Fumiyuki Adachi

Inventor： Changming Zhou ,  Xuping Zhou ,  Guoliang Shou ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC: H04B169

CPC classification number: H04B1/7093

Abstract: An output of analog complex matched filter is simplified to be a one dimensional signal such as electrical power. Multi-path detection is performed by the simplified signal. The output of the matched filter is received and processed only when peaks occur in the one dimensional signal.

Abstract translation: 模拟复合匹配滤波器的输出被简化为诸如电功率的一维信号。 通过简化信号执行多路径检测。 匹配滤波器的输出仅在一维信号中出现峰值时才被接收和处理。

公开(公告)号：US06169771A

公开(公告)日：2001-01-02

申请号：US09014264

申请日：1998-01-27

Applicant: Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Xiaoling Oin ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

Inventor： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Xiaoling Oin ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

IPC: H04L2706

CPC classification number: H03H17/0254 ,  H04B1/7093

Abstract: In one aspect, the present invention provides a low power consumption matched filter. The signal received at an input terminal is input to a shift register having stages equal to the spread code length number after conversion into digital signals in an A/D converter. The outputs of the shift register stages are input to XOR circuits set corresponding to each stage, so that XOR operations are performed between the outputs and corresponding spread code bits d1 to dN. The outputs of the XOR circuits are analogously added in an analog adder and output from an output terminal. In another aspect, a filter circuit uses an analog operation circuit to prevent lowered operational accuracy caused by residual charge. Input analog signals successively undergo sampling and holding in sample-and-hold circuits, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in an addition circuit. Sample data transmission error storage is prevented by shifting coefficients in the shift register. Sample-and-hold circuits and multiplication circuits are formed by analog operation circuits, and each include a switch for canceling the residual charge. The sample-and-hold circuits and multiplication circuits normally working are refreshed sequentially by providing circuits for replacing their function. The addition circuit is refreshed in the same way.

Abstract translation: 一方面，本发明提供一种低功耗匹配滤波器。 在A / D转换器转换成数字信号之后，在输入端接收的信号被输入到具有等于扩展码长度数的级的移位寄存器。 移位寄存器级的输出被输入到对应于每一级的XOR电路，从而在输出和对应的扩展码位d1至dN之间执行异或运算。 XOR电路的输出类似地添加到模拟加法器中并从输出端子输出。 另一方面，滤波器电路使用模拟运算电路来防止由剩余电荷引起的运算精度降低。 输入模拟信号在采样保持电路中连续进行采样和保持，乘以乘法电路存储在移位寄存器中的系数，并加入加法电路。 通过移位寄存器中的系数来防止采样数据传输错误存储。 采样保持电路和乘法电路由模拟操作电路形成，并且每个都包括用于消除剩余电荷的开关。 正常工作的采样保持电路和乘法电路通过提供更换其功能的电路依次刷新。 加法电路以相同的方式刷新。

公开(公告)号：US6094667A

公开(公告)日：2000-07-25

申请号：US3507

申请日：1998-01-06

Applicant: Xuping Zhou ,  Changming Zhou ,  Guoliang Shou

Inventor： Xuping Zhou ,  Changming Zhou ,  Guoliang Shou

IPC: H03H21/00 ,  H03H17/00 ,  H04B1/10 ,  H04L25/03 ,  G06F17/10 ,  H04L27/00

CPC classification number: H03H17/00 ,  H04L25/03834

Abstract: In a method is disclosed for transmitting and receiving a transmission data signal, after the transmission data signal is generated, it is modulated by a first time spread root Nyquist filter to generate a transmission signal. The signal is then transmitted and received, whereupon the signal is transformed into a baseband signal. The baseband signal is then demodulated through a second time spread root Nyquist filter to revive the transmission data signal. An apparatus is also disclosed that performs this method. In addition, methods of separately transmitting and receiving signals are also described.

Abstract translation: 公开了一种用于发送和接收发送数据信号的方法，在发送数据信号产生之后，由第一时间扩展根奈奎斯特滤波器对其进行调制以产生发送信号。 然后发送和接收信号，由此将信号变换成基带信号。 然后通过第二时间扩展根奈奎斯特滤波器对基带信号进行解调，以恢复发送数据信号。 还公开了执行该方法的装置。 此外，还描述了单独发送和接收信号的方法。

公开(公告)号：US6084922A

公开(公告)日：2000-07-04

申请号：US61097

申请日：1998-04-16

Applicant: Changming Zhou ,  Xuping Zhou ,  Guoliang Shou

Inventor： Changming Zhou ,  Xuping Zhou ,  Guoliang Shou

IPC: H04B1/26 ,  H04B1/16 ,  H04B7/26 ,  H04J1/00 ,  H04M1/73 ,  H04W52/02 ,  H04L27/06

CPC classification number: H04B1/1615 ,  H04W52/029

Abstract: A waiting circuit which is utilized in a mobile communication system. The waiting circuit detects a predetermined signal from a base station. The waiting circuit starts other circuits in the mobile communication system which are in a sleep mode when the predetermined signal is received. The predetermined signal is generated in the base station. The predetermined signal has a speed equal to a predetermined symbol rate and is modulated to be an intermediate frequency signal. The intermediate frequency signal is sampled in response to a sampling clock that has a speed equal to an integer times the symbol rate. The sampled intermediate frequency signal is input to a match filter which multiplies the sample signal by a predetermined sequence of coefficients.

Abstract translation: 一种在移动通信系统中使用的等待电路。 等待电路检测来自基站的预定信号。 当接收到预定信号时，等待电路开始处于睡眠模式的移动通信系统中的其他电路。 在基站中产生预定信号。 预定信号具有等于预定符号速率的速度并被调制成中频信号。 响应于具有等于符号率的整数倍的速度的采样时钟对中频信号进行采样。 采样的中频信号被输入到将采样信号乘以预定系数序列的匹配滤波器。