公开(公告)号：US20090179329A1

公开(公告)日：2009-07-16

申请号：US12345611

申请日：2008-12-29

申请人： Cheol Mo Jeong ,  Eun Soo Kim ,  Seung Hee Hong

发明人： Cheol Mo Jeong ,  Eun Soo Kim ,  Seung Hee Hong

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to semiconductor devices and a method of fabricating the same. According to a method of manufacturing semiconductor devices, there is first provided a semiconductor substrate in which a first pre-metal dielectric layer including trenches is formed. A diffusion barrier layer is formed on the entire surface including the trenches. A metal layer is formed on the diffusion barrier layer including the trenches, thereby gap-filling the trenches. A polish etching process is performed on the metal layer and the diffusion barrier layer so that the diffusion barrier layer and the metal layer remain within the trenches. An etching process of lowering a height of the metal layer is performed in order to increase a distance between metal lines. A capping layer is formed on the entire surface including exposed sidewalls of the first pre-metal dielectric layer. A second pre-metal dielectric layer is formed over the capping layer.

摘要翻译： 本发明涉及半导体器件及其制造方法。 根据制造半导体器件的方法，首先提供其中形成包括沟槽的第一预金属电介质层的半导体衬底。 在包括沟槽的整个表面上形成扩散阻挡层。 在包括沟槽的扩散阻挡层上形成金属层，从而间隙填充沟槽。 在金属层和扩散阻挡层上进行抛光蚀刻工艺，使得扩散阻挡层和金属层保留在沟槽内。 执行降低金属层的高度的蚀刻工艺，以增加金属线之间的距离。 在包括第一预金属介电层的暴露的侧壁的整个表面上形成覆盖层。 在覆盖层上方形成第二预金属介电层。

公开(公告)号：US07517793B2

公开(公告)日：2009-04-14

申请号：US11753543

申请日：2007-05-24

申请人： Seung Hee Hong ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Soo Kim

发明人： Seung Hee Hong ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Soo Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/28562 ,  H01L21/32131 ,  H01L21/76879 ,  H01L21/76882

摘要： A method of forming a metal wire in a semiconductor device includes performing a first etching process on an insulating layer formed on a semiconductor substrate to form a trench and an insulating layer pattern, the insulating layer pattern defining the trench. A barrier metal layer is formed over the insulating layer pattern and the trench. A second etching process is performed on the barrier metal layer to expose upper corners of the trench while leaving the trench substantially covered with the barrier metal layer. A metal layer is formed over the barrier metal layer in the trench. A heat treatment process is performed for reflowing the metal layer. The metal layer is planarized.

摘要翻译： 在半导体器件中形成金属线的方法包括对形成在半导体衬底上的绝缘层进行第一蚀刻工艺以形成沟槽和绝缘层图案，绝缘层图案限定沟槽。 在绝缘层图案和沟槽之上形成阻挡金属层。 在阻挡金属层上进行第二蚀刻工艺以暴露沟槽的上角，同时留下基本上被阻挡金属层覆盖的沟槽。 在沟槽中的阻挡金属层的上方形成有金属层。 进行用于回流金属层的热处理工艺。 金属层被平坦化。

公开(公告)号：US20090098727A1

公开(公告)日：2009-04-16

申请号：US12147196

申请日：2008-06-26

申请人： Seung Hee Hong ,  Cheol Mo Jeong ,  Eun Soo Kim

发明人： Seung Hee Hong ,  Cheol Mo Jeong ,  Eun Soo Kim

IPC分类号： H01L21/768

CPC分类号： H01L21/76846 ,  H01L21/7684 ,  H01L21/76882 ,  H01L23/53214 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed herein is a method of forming a metal line of a semiconductor device. According to the method, a contact hole is formed in a second insulating layer over a semiconductor substrate. A first barrier metal layer, including a TiN layer, is formed on a surface of the second insulating layer. The first barrier metal layer is formed such that the TiN layer is formed thinner at a bottom of the contact hole than on sidewalls and a top surface of the second insulating layer. A first metal layer is formed on the first barrier metal layer, including on the contact hole. Thermal treatment is carried to gap-fill the contact hole as the first metal layer is reflown and smooth. A second metal layer is formed on the first metal layer. The second metal layer to form an upper metal line.

摘要翻译： 本文公开了形成半导体器件的金属线的方法。 根据该方法，在半导体衬底上的第二绝缘层中形成接触孔。 在第二绝缘层的表面上形成包括TiN层的第一阻挡金属层。 第一阻挡金属层形成为使得TiN层在接触孔的底部比在侧壁和第二绝缘层的顶表面上形成得更薄。 第一金属层形成在第一阻挡金属层上，包括在接触孔上。 当第一金属层被退光并且光滑时，进行热处理以间隙填充接触孔。 第二金属层形成在第一金属层上。 第二金属层形成上金属线。

公开(公告)号：US07507628B2

公开(公告)日：2009-03-24

申请号：US11751015

申请日：2007-05-19

申请人： Seung Hee Hong ,  Cheol Mo Jeong ,  Eun Soo Kim

发明人： Seung Hee Hong ,  Cheol Mo Jeong ,  Eun Soo Kim

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/42336 ,  H01L21/763 ,  H01L27/115 ,  H01L27/11521

摘要： A method of manufacturing a non-volatile memory device includes forming a trench using the shallow trench isolation (STI) method; forming a first insulating layer on a semiconductor device including the trench; forming a conductive layer on the semiconductor device including the trench; etching the conductive layer to form a conductive layer for a floating gate on an active area and to form a recessed gap-fill conductive layer on an isolation layer; forming a second insulating layer and a third insulating layer on the semiconductor substrate including the gap fill conductive layer and the conductive layer for the floating gate; and etching a portion of the second insulating layer and the third insulating layer to form an isolation structure consisting of the gap fill conductive layer, the second insulating layer and the third insulating layer on the isolation area.

摘要翻译： 制造非易失性存储器件的方法包括使用浅沟槽隔离（STI）法形成沟槽; 在包括所述沟槽的半导体器件上形成第一绝缘层; 在包括沟槽的半导体器件上形成导电层; 蚀刻导电层以在有源区上形成用于浮栅的导电层，并在隔离层上形成凹陷间隙填充导电层; 在包括间隙填充导电层和用于浮置栅极的导电层的半导体衬底上形成第二绝缘层和第三绝缘层; 以及蚀刻所述第二绝缘层和所述第三绝缘层的一部分，以形成由隔离区上的间隙填充导电层，第二绝缘层和第三绝缘层组成的隔离结构。

公开(公告)号：US20090065940A1

公开(公告)日：2009-03-12

申请号：US11951379

申请日：2007-12-06

申请人： Eun Soo Kim ,  Cheol Mo Jeong ,  Seung Hee Hong

发明人： Eun Soo Kim ,  Cheol Mo Jeong ,  Seung Hee Hong

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/485 ,  H01L21/76877 ,  H01L21/76885 ,  H01L27/11521 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to a method of forming a metal wiring of a semiconductor device, a contact plug is formed at height lower than the contact hole, which is formed on an interlayer insulation layer, and then a metal wiring is formed over the contact plug and interlayer insulation layer to completely fill inside of the contact hole, decreasing process difficulty, ensuring reproducibility, and improving electrical property.

摘要翻译： 根据形成半导体器件的金属布线的方法，在形成在层间绝缘层上的接触孔的下方形成接触插塞，然后在接触插塞和层间绝缘层上形成金属布线 层完全填充接触孔内部，降低工艺难度，确保再现性，并提高电气性能。

公开(公告)号：US20090001581A1

公开(公告)日：2009-01-01

申请号：US11951245

申请日：2007-12-05

申请人： Eun Soo KIM ,  Cheol Mo Jeong ,  Seung Hee Hong

发明人： Eun Soo KIM ,  Cheol Mo Jeong ,  Seung Hee Hong

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53223 ,  H01L21/76849 ,  H01L21/76868 ,  H01L21/76882 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal line of a semiconductor device includes an insulating layer in which damascene patterns have been formed, a first metal layer formed on sidewalls and bottom surfaces of the damascene patterns, a second metal layer formed on the first metal layer within the damascene patterns and having a lower resistance than the first metal layer, and a third metal layer formed on the second metal layer.

摘要翻译： 半导体器件的金属线包括其中形成有镶嵌图案的绝缘层，形成在镶嵌图案的侧壁和底表面上的第一金属层，形成在镶嵌图案内的第一金属层上的第二金属层，并且具有 比第一金属层低的电阻，以及形成在第二金属层上的第三金属层。

公开(公告)号：US20080064204A1

公开(公告)日：2008-03-13

申请号：US11646925

申请日：2006-12-27

申请人： Eun Soo Kim ,  Cheol Mo Jeong ,  Seung Hee Hong

发明人： Eun Soo Kim ,  Cheol Mo Jeong ,  Seung Hee Hong

IPC分类号： H01L21/44

CPC分类号： H01L21/76882 ,  H01L21/76838 ,  H01L21/76865 ,  H01L21/76879

摘要： A first conductive layer is formed over a substrate in which contact holes are formed in an interlayer insulating layer. The first conductive layer is melted by an annealing process, thus coating the lower sidewalls of the contact holes and partially filling the contact holes. A second conductive layer is deposited with a method having selectivity with respect to the same material as the first conductive layer, thus fully filling the contact holes. A metal line is formed on the second conductive layer. The contact holes are completely filled with a conductive material and the load of a CMP process can be alleviated. Accordingly, the electrical characteristics of a device can be improved, process reliability can be improved, and process repeatablity can be improved.

摘要翻译： 在层间绝缘层中形成有接触孔的基板上形成第一导电层。 第一导电层通过退火工艺熔化，从而涂覆接触孔的下侧壁并部分填充接触孔。 以与第一导电层相同的材料具有选择性的方法沉积第二导电层，从而完全填充接触孔。 金属线形成在第二导电层上。 接触孔完全充满导电材料，可以减轻CMP工艺的负荷。 因此，可以提高器件的电气特性，提高工艺可靠性，提高加工的可重复性。

公开(公告)号：US07892919B2

公开(公告)日：2011-02-22

申请号：US12163328

申请日：2008-06-27

申请人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho

发明人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho

IPC分类号： H01L21/8242

CPC分类号： H01L21/76232

摘要： The invention discloses a method of forming an isolation layer in a semiconductor device. The method includes providing a semiconductor substrate having a trench formed therein; forming a first insulating layer in the trench; and forming a densified second insulating layer on the first insulating layer. In the above method, a void is not generated in the isolation layer so a bending phenomenon of an active region can be reduced or prevented to improve an electrical characteristic of the semiconductor.

摘要翻译： 本发明公开了一种在半导体器件中形成隔离层的方法。 该方法包括提供其中形成有沟槽的半导体衬底; 在沟槽中形成第一绝缘层; 以及在所述第一绝缘层上形成致密的第二绝缘层。 在上述方法中，在隔离层中不会产生空隙，因此可以减少或防止有源区的弯曲现象来改善半导体的电特性。

公开(公告)号：US20100304549A1

公开(公告)日：2010-12-02

申请号：US12815317

申请日：2010-06-14

申请人： Cha Deok DONG ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

发明人： Cha Deok DONG ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.

摘要翻译： 形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。 每个第一沟槽的侧壁和底表面被自由基氧化过程氧化以形成第一氧化物层。 在每个第一沟槽的侧壁上形成防氧化间隔物。 第二沟槽形成在对应的第一沟槽下方的隔离区域中，其中每个第二沟槽比相应的第一沟槽更窄和更深。 第二沟槽填充有第二氧化物层。 第一沟槽填充有绝缘层。

公开(公告)号：US20080003754A1

公开(公告)日：2008-01-03

申请号：US11646777

申请日：2006-12-28

申请人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung

发明人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.

摘要翻译： 一种形成闪速存储器件的栅极的方法，包括以下步骤：在半导体衬底上形成栅极并在栅极的整个表面上形成氧化物层，在间隔物的氧化物层的侧壁上形成氮化物层 形成，进行抛光处理使得栅极的顶表面露出，然后剥离氮化物层以形成开口，在开口的侧壁上形成阻挡金属层，并在开口中形成钨层。