公开(公告)号：US09344105B2

公开(公告)日：2016-05-17

申请号：US14890160

申请日：2014-05-05

申请人： China Electronic Technology Corporation, 24th Research Institute

发明人： Ting Li ,  Ru-Zhang Li ,  Yong Zhang ,  Zheng-Bo Huang ,  Guang-Bing Chen ,  Jian-An Wang ,  Yu-Xin Wang ,  Dong-Bing Fu ,  Yan Wang ,  Xu Wang

IPC分类号： H03M1/06 ,  H03M1/42 ,  H03M1/12

CPC分类号： H03M1/0675 ,  H03M1/0678 ,  H03M1/1061 ,  H03M1/1245 ,  H03M1/42 ,  H03M1/468 ,  H03M1/687

摘要： A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors.

摘要翻译： 提供了逐次逼近的模数转换器及其转换方法，逐次逼近模数转换器包括具有冗余位的分段多级电容器阵列，比较器，加权存储电路，代码重构 电路和控制逻辑电路。 逐次逼近模数转换器有助于降低电路设计的复杂性，具有体积小，功耗低的特点。 没有辅助电容阵列，开关和控制逻辑，该电路可以用来精确测量和纠正电容器失配误差。

公开(公告)号：US09336347B2

公开(公告)日：2016-05-10

申请号：US14396737

申请日：2013-11-28

申请人： China Electronic Technology Corporation, 24th Research Institute

发明人： Yan Wang ,  Yu-Xin Wang ,  Gang-Yi Hu ,  Ting Li ,  Tao Liu ,  Guang-Bing Chen

IPC分类号： H01G4/38 ,  G06F17/50 ,  H01G15/00 ,  H03M1/16 ,  H03M1/44

CPC分类号： G06F17/5072 ,  G06F17/50 ,  G06F17/5077 ,  H01G4/38 ,  H01G15/00 ,  H03M1/164 ,  H03M1/442

摘要： A layout design method is provided for generating capacitor arrays being described in four steps: first, the wiring mode of unit capacitors is defined allowing the wire being connected to the upper plate to parallel that to the lower one, second, a capacitor array layout is designed with capacitors being distributed in Mh lines, Mh is the maximum of capacitors' lines, the line numbers of Class 1 to Class K capacitors are defined in the unilateral capacitor array, third, the wiring mode is set for capacitor array making sure the lengths of the wires to the upper and lower plates of unit capacitors are equal, at last, parasitic parameters are characterized in ways that verify the layout. A capacitor array is provided as well. By eliminating capacitance mismatching caused by parasitic capacitance, the method works to generate a well-matched capacitor array in an easy and efficient way.

摘要翻译： 提供一种用于产生电容器阵列的布局设计方法，其分为四个步骤：首先，确定单元电容器的布线模式，允许将导线连接到上板与下板平行;第二，电容器阵列布局为 设计有电容分布在Mh线，Mh是电容器线的最大值，单相电容器阵列中定义了1类至K类电容器的线数;第三，为电容器阵列设置了布线模式，确保长度 到单元电容器的上板和下板的电线相等，最后，寄生参数以验证布局的方式进行表征。 还提供电容器阵列。 通过消除由寄生电容引起的电容失配，该方法可以以简单有效的方式产生良好匹配的电容器阵列。