公开(公告)号：US09337834B2

公开(公告)日：2016-05-10

申请号：US14355580

申请日：2012-11-19

申请人： China Electronic Technology Corporation, 24th Research Institute

发明人： Xi Chen ,  Gang-Yi Hu ,  Xue-Liang Xu ,  Xing-Fa Huang ,  Liang Li ,  Xiao-Feng Shen ,  Ming-Yuan Xu ,  Lei Zhang ,  Yan Wang ,  Rong-Ke Ye ,  You-Hua Wang ,  Xu Huang ,  Jiao-Xue Li

IPC分类号： H03K17/687 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/003 ,  H03K19/094

CPC分类号： H03K19/0005 ,  H03K19/0013 ,  H03K19/00361 ,  H03K19/01714 ,  H03K19/018521 ,  H03K19/09432

摘要： A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits' transconductance and output impedance resulting from input signals' variation. In doing so, the linearity of CMOS input buffer is improved. The buffer circuit includes a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance. The buffer circuit is fabricated in standard CMOS process, featuring low cost, simplicity and strong linearity at high frequency. It has wide applications in analog and hybrid analog-digital CMOS ICs requiring high linearity input buffer.

摘要翻译： 提供高线性CMOS输入缓冲电路，用于中和由输入信号变化引起的跟随器电路的跨导和输出阻抗的非线性。 这样做可以提高CMOS输入缓冲器的线性度。 缓冲电路包括CMOS输入跟随器电路，跟随器晶体管的线性改善电路，电流源负载和负载阻抗的线性改善电路。 缓冲电路采用标准CMOS工艺制造，具有成本低，简便性强，线性高的特点。 它在需要高线性输入缓冲器的模拟和混合模拟数字CMOS IC中具有广泛的应用。

公开(公告)号：US20140152348A1

公开(公告)日：2014-06-05

申请号：US14115630

申请日：2012-09-27

申请人： China Electronic Technology Corporation, 24th Research Institute

发明人： Rong-Bin Hu ,  Gang-Yi Hu ,  Dong-Bing Fu ,  Yong-Lu Wang ,  Zheng-Ping Zhang ,  Can Zhu ,  Yu-Han Gao ,  Lei Zhang ,  Rong-Ke Ye

IPC分类号： H03K3/01

CPC分类号： H03K3/01 ,  G05F3/30

摘要： A BiCMOS current reference circuit includes a reference core, a startup circuit, and a reference current output circuit. The reference core contains a current mirror, a positive temperature coefficient current generator, and a negative temperature coefficient current generator. The current mirror generates matching branch current. The positive and negative temperature coefficient currents were added in certain proportion to generate a reference current with zero temperature coefficient at room temperature. The startup circuit starts the reference core at power-on. The reference current output circuit proportionably outputs reference current generated by the reference core. Compared with the conventional voltage reference, the circuit uses current conveying technique, so it won't be affected by DC voltage drops of power supply network, and it features low transmission loss, good matching, excellent temperature stability, small chip size and auto-startup at power-on. It's preferably suitable for applications where A/D and D/A converters require accurate reference signals.

摘要翻译： BiCMOS电流参考电路包括参考磁芯，启动电路和参考电流输出电路。 参考磁芯包含电流镜，正温度系数电流发生器和负温度系数电流发生器。 当前镜像生成匹配分支电流。 以一定比例加入正温度系数和负温度系数电流，以产生室温下零温度系数的参考电流。 启动电路在上电时启动参考内核。 参考电流输出电路按比例输出由参考磁芯产生的参考电流。 与常规电压基准相比，电路采用电流传输技术，不受电网直流电压下降的影响，传输损耗低，匹配匹配好，温度稳定性好，芯片尺寸小， 开机启动 它优选适用于A / D和D / A转换器需要精确参考信号的应用。

公开(公告)号：US20170331486A1

公开(公告)日：2017-11-16

申请号：US15521178

申请日：2015-05-21

申请人： China Electronic Technology Corporation, 24th Research Institute

发明人： Dai-Guo Xu ,  Shi-Liu Xu ,  Gang-Yi Hu ,  Guang-Bing Chen ,  Jian-An Wang

IPC分类号： H03M1/08 ,  H03M1/10 ,  H03M1/20 ,  H03M1/28

CPC分类号： H03M1/0809 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1023 ,  H03M1/12 ,  H03M1/144 ,  H03M1/204 ,  H03M1/282

摘要： The present invention pertains to a high-speed successive approximation analog-to-digital converter of two bits per circle, includes three switches, two capacitor arrays, three comparators, an encoding circuit, a first switch array corresponding to the first capacitor array, a second switch array corresponding to the second capacitor array, a shifting register and a digital correction unit. The analog-to-digital converter, featuring doubled speed, realizes a successive approximation process without any fault when a high-bit large capacitor is unsettled. Thus no redundancy bit capacitor is required to compensate for unsettled pre-stage large capacitor. By using the encoding circuit, a thermometer code is converted into a binary code effectively, and inherent errors of comparators are reduced by the randomization of three comparators.

公开(公告)号：US09667267B2

公开(公告)日：2017-05-30

申请号：US15121381

申请日：2015-01-28

申请人： China Electronic Technology Corporation, 24th Research Institute

发明人： Yan Wang ,  Gang-Yi Hu ,  Tao Liu ,  Yu-Xin Wang ,  Jian-An Wang ,  Dong-Bing Fu ,  Ting Li ,  Guang-Bing Chen

IPC分类号： H03M1/20 ,  H03M1/10 ,  H03M1/12 ,  H03M1/46 ,  H03M1/06 ,  H03M1/74

CPC分类号： H03M1/201 ,  H03M1/0641 ,  H03M1/1009 ,  H03M1/1061 ,  H03M1/1245 ,  H03M1/46 ,  H03M1/742

摘要： A dither circuit for high-resolution analog-to-digital converters (ADCs) is presented, including a settable pseudorandom sequence generator, a trimming module, a trimmable digital-to-analog conversion circuit, a dither introduced circuit and a dither elimination circuit, wherein the settable pseudorandom sequence generator works to generate pseudorandom sequence signal uncorrelated to analog input signal and its output can be set, of which n bit output is taken as digital dither signal and n can be less than the quantization bit of the ADC; the trimming module works to determine the trimming signals for the trimmable digital-to-analog conversion circuit to convert the digital dither signal into analog dither signal precisely; the dither introduced circuit works to introduce the analog dither signal to the ADC; the dither elimination circuit works to remove the digital dither signal from the output of ADC. The dither circuit features less complexity and better dynamic performance for high-resolution ADC.

公开(公告)号：US10735009B2

公开(公告)日：2020-08-04

申请号：US16475117

申请日：2016-06-01

申请人： CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

发明人： Ting Li ,  Gang-Yi Hu ,  Ru-Zhang Li ,  Jian-An Wang ,  Yong Zhang ,  Zheng-Bo Huang ,  Guang-Bing Chen ,  Yu-Xin Wang ,  Dong-Bing Fu ,  Yan Wang ,  Jun Yuan

IPC分类号： H03M1/06

摘要： A sampling device includes a switch capacitor circuit. First ends of two switches are respectively connected to an input signal. Second end of the first switch is connected to an upper plate of a first capacitor. Second end of the second switch is connected to a lower plate of a second capacitor. A connection node connecting a lower plate of the first capacitor to an upper plate of the second capacitor is connected to a power source. The first ends of a third switch and a fourth switch are respectively connected to an input common-mode voltage. A second end of the third switch is connected to the upper plate of the first capacitor. A second end of the fourth switch is connected to the lower plate of the second capacitor. The connection node is connected to the power source. Thus, an output common-mode voltage of the sampling device is adjustable.

公开(公告)号：US20150102848A1

公开(公告)日：2015-04-16

申请号：US14355580

申请日：2012-11-19

申请人： China Electronic Technology Corporation, 24th Research Institute

发明人： Xi Chen ,  Gang-Yi Hu ,  Xue-Liang Xu ,  Xing-Fa Huang ,  Liang Li ,  Xiao-Feng Shen ,  Ming-Yuan Xu ,  Lei Zhang ,  Yan Wang ,  Rong-Ke Ye ,  You-Hua Wang ,  Xu Huang ,  Jiao-Xue Li

IPC分类号： H03K19/00 ,  H03K19/094 ,  H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/0005 ,  H03K19/0013 ,  H03K19/00361 ,  H03K19/01714 ,  H03K19/018521 ,  H03K19/09432

摘要： A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits' transconductance and output impedance resulting from input signals' variation. In doing so, the linearity of CMOS input buffer is improved. The buffer circuit includes a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance. The buffer circuit is fabricated in standard CMOS process, featuring low cost, simplicity and strong linearity at high frequency. It has wide applications in analog and hybrid analog-digital CMOS ICs requiring high linearity input buffer.

摘要翻译： 提供高线性CMOS输入缓冲电路，用于中和由输入信号变化引起的跟随器电路的跨导和输出阻抗的非线性。 这样做可以提高CMOS输入缓冲器的线性度。 缓冲电路包括CMOS输入跟随器电路，跟随器晶体管的线性改善电路，电流源负载和负载阻抗的线性改善电路。 缓冲电路采用标准CMOS工艺制造，具有成本低，简便性强，线性高的特点。 它在需要高线性输入缓冲器的模拟和混合模拟数字CMOS IC中具有广泛的应用。

公开(公告)号：US10735008B2

公开(公告)日：2020-08-04

申请号：US16476106

申请日：2016-06-27

申请人： CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

发明人： Rong-Bin Hu ,  Yong-Lu Wang ,  Gang-Yi Hu ,  He-Quan Jiang ,  Zheng-Ping Zhang ,  Guang-Bing Chen ,  Dong-Bing Fu ,  Yu-Xin Wang ,  Lei Zhang ,  Rong-Ke Ye ,  Can Zhu ,  Yu-Han Gao

IPC分类号： H03M1/06 ,  H03K5/24

摘要： A comparator offset voltage self-correction circuit is disclosed. A comparator offset voltage which is caused by the semiconductor process parameter randomness also has randomness. Due to the randomness of the comparator offset voltage, a reference voltage of a parallel comparator in a parallel-conversion-type analog-to-digital converter is uncertain. If the comparator offset voltage is large, the parallel-conversion-type analog-to-digital converter may even have a functional error. The comparator offset voltage self-correction circuit provided in the present invention can correct a random offset voltage of a comparator to meet requirements. Therefore, by means of the circuit and a method provided in the present invention, adverse influence of the random offset of the comparator on the function and the performance of the parallel-conversion-type analog-to-digital converter is eliminated, thereby greatly improving the speed and the performance of the analog-to-digital converter, in particular the parallel-conversion-type analog-to-digital converter.

公开(公告)号：US10666243B2

公开(公告)日：2020-05-26

申请号：US16475123

申请日：2016-07-07

申请人： CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE

发明人： Dai-Guo Xu ,  Gang-Yi Hu ,  Ru-Zhang Li ,  Jian-An Wang ,  Guang-Bing Chen ,  Yu-Xin Wang ,  Dong-Bing Fu ,  Tao Liu

IPC分类号： H03K5/00 ,  H03K5/24 ,  H03K19/00 ,  H03K19/003

摘要： A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.

公开(公告)号：US09966967B2

公开(公告)日：2018-05-08

申请号：US15521178

申请日：2015-05-21

申请人： China Electronic Technology Corporation, 24th Research Institute

发明人： Dai-Guo Xu ,  Shi-Liu Xu ,  Gang-Yi Hu ,  Guang-Bing Chen ,  Jian-An Wang

IPC分类号： H03M1/12 ,  H03M1/08 ,  H03M1/20 ,  H03M1/28 ,  H03M1/10 ,  H03M1/06 ,  H03M1/00

CPC分类号： H03M1/0809 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1023 ,  H03M1/12 ,  H03M1/144 ,  H03M1/204 ,  H03M1/282

摘要： A high-speed successive approximation analog-to-digital converter of two bits per cycle, includes three switches, two capacitor arrays, three comparators, an encoding circuit, a first switch array corresponding to the first capacitor array, a second switch array corresponding to the second capacitor array, a shifting register and a digital correction unit. The analog-to-digital converter, featuring doubled speed, realizes a successive approximation process without any fault when a high-bit large capacitor is unsettled. Thus no redundancy bit capacitor is required to compensate for unsettled pre-stage large capacitor. By using the encoding circuit, a thermometer code is converted into a binary code effectively, and inherent errors of comparators are reduced by the randomization of three comparators.

公开(公告)号：US10128830B2

公开(公告)日：2018-11-13

申请号：US15318975

申请日：2014-04-17

申请人： China Electronic Technology Corporation, 24th Research Institute

发明人： Rong-Bin Hu ,  Guang-Bing Chen ,  Gang-Yi Hu ,  Yong-Lu Wang ,  Zheng-Ping Zhang ,  Can Zhu ,  Rong-Ke Ye ,  Lei Zhang ,  Yu-Han Gao

IPC分类号： G11C27/02 ,  H03K17/082

摘要： A track and hold circuit comprises an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode and a sampling capacitor. The input buffer amplifier receives an input signal. In a track phase, the sampling switch is electrically connected to an emitter electrode of the drive triode; the input signal charges the sampling capacitor after being buffered by the input buffer amplifier, amplified without distortion by the unit gain amplifier module and driven by the drive triode. In a hold phase, the sampling switch is electrically connected to a base electrode of the drive triode; the base voltage of the drive triode is pulled down until the drive triode is cut off; electrical charges on the sampling capacitor are thereby held, causing the signal to be held on the sampling capacitor.