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公开(公告)号：US20170331486A1
公开(公告)日：2017-11-16
申请号：US15521178
申请日：2015-05-21
发明人： Dai-Guo Xu , Shi-Liu Xu , Gang-Yi Hu , Guang-Bing Chen , Jian-An Wang
CPC分类号： H03M1/0809 , H03M1/00 , H03M1/0695 , H03M1/1023 , H03M1/12 , H03M1/144 , H03M1/204 , H03M1/282
摘要： The present invention pertains to a high-speed successive approximation analog-to-digital converter of two bits per circle, includes three switches, two capacitor arrays, three comparators, an encoding circuit, a first switch array corresponding to the first capacitor array, a second switch array corresponding to the second capacitor array, a shifting register and a digital correction unit. The analog-to-digital converter, featuring doubled speed, realizes a successive approximation process without any fault when a high-bit large capacitor is unsettled. Thus no redundancy bit capacitor is required to compensate for unsettled pre-stage large capacitor. By using the encoding circuit, a thermometer code is converted into a binary code effectively, and inherent errors of comparators are reduced by the randomization of three comparators.
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公开(公告)号：US09667267B2
公开(公告)日：2017-05-30
申请号：US15121381
申请日：2015-01-28
发明人： Yan Wang , Gang-Yi Hu , Tao Liu , Yu-Xin Wang , Jian-An Wang , Dong-Bing Fu , Ting Li , Guang-Bing Chen
CPC分类号： H03M1/201 , H03M1/0641 , H03M1/1009 , H03M1/1061 , H03M1/1245 , H03M1/46 , H03M1/742
摘要： A dither circuit for high-resolution analog-to-digital converters (ADCs) is presented, including a settable pseudorandom sequence generator, a trimming module, a trimmable digital-to-analog conversion circuit, a dither introduced circuit and a dither elimination circuit, wherein the settable pseudorandom sequence generator works to generate pseudorandom sequence signal uncorrelated to analog input signal and its output can be set, of which n bit output is taken as digital dither signal and n can be less than the quantization bit of the ADC; the trimming module works to determine the trimming signals for the trimmable digital-to-analog conversion circuit to convert the digital dither signal into analog dither signal precisely; the dither introduced circuit works to introduce the analog dither signal to the ADC; the dither elimination circuit works to remove the digital dither signal from the output of ADC. The dither circuit features less complexity and better dynamic performance for high-resolution ADC.
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公开(公告)号：US10735009B2
公开(公告)日：2020-08-04
申请号：US16475117
申请日：2016-06-01
发明人： Ting Li , Gang-Yi Hu , Ru-Zhang Li , Jian-An Wang , Yong Zhang , Zheng-Bo Huang , Guang-Bing Chen , Yu-Xin Wang , Dong-Bing Fu , Yan Wang , Jun Yuan
IPC分类号： H03M1/06
摘要： A sampling device includes a switch capacitor circuit. First ends of two switches are respectively connected to an input signal. Second end of the first switch is connected to an upper plate of a first capacitor. Second end of the second switch is connected to a lower plate of a second capacitor. A connection node connecting a lower plate of the first capacitor to an upper plate of the second capacitor is connected to a power source. The first ends of a third switch and a fourth switch are respectively connected to an input common-mode voltage. A second end of the third switch is connected to the upper plate of the first capacitor. A second end of the fourth switch is connected to the lower plate of the second capacitor. The connection node is connected to the power source. Thus, an output common-mode voltage of the sampling device is adjustable.
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公开(公告)号：US09588539B2
公开(公告)日：2017-03-07
申请号：US14785349
申请日：2014-04-02
发明人： Rong-Ke Ye , Can Zhu , Gnag-Yi Hu , Lei Zhang , Rong-Bin Hu , Yu-Han Gao , Zheng-Ping Zhang , Yong-Lu Wang , Guang-Bing Chen
摘要： A band-gap reference circuit includes a proportioned current generating circuit, a startup circuit, a current mirror circuit, a high-order temperature compensation generating circuit and a reference generating circuit. The proportioned current generating circuit is configured to generate a current in direct proportion to the absolute temperature. The startup circuit is configured to start up the proportioned current generating circuit when the startup circuit is power on. The current mirror circuit is configured to reproduce a current which is the same as the current in direct proportion to the absolute temperature. The high-order temperature compensation generating circuit is configured to generate a compensation current of high-order temperature coefficient. The reference generating circuit is configured to add the voltage which is generated by the proportioned current generating circuit to a voltage of negative temperature coefficient according to a certain proportion, and output a reference voltage of zero temperature coefficient.
摘要翻译： 带隙基准电路包括比例电流产生电路，启动电路，电流镜电路，高阶温度补偿发生电路和基准发生电路。 成比例的电流产生电路被配置为产生与绝对温度成正比的电流。 启动电路被配置为在启动电路接通电源时启动成比例的电流产生电路。 电流镜电路被配置为再现与绝对温度成正比的电流相同的电流。 高阶温度补偿发生电路被配置为产生高阶温度系数的补偿电流。 参考产生电路被配置为根据一定比例将由比例电流产生电路产生的电压加到负温度系数的电压，并输出零温度系数的参考电压。
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公开(公告)号：US10971929B2
公开(公告)日：2021-04-06
申请号：US16310451
申请日：2016-06-22
发明人： Yan Wang , Tao Liu , Guang-Bing Chen , Yu-Xin Wang , Dong-Bing Fu , Yu-Jun Yang , Liang Chen , Yang Pu
摘要： The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.
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公开(公告)号：US10735008B2
公开(公告)日：2020-08-04
申请号：US16476106
申请日：2016-06-27
发明人： Rong-Bin Hu , Yong-Lu Wang , Gang-Yi Hu , He-Quan Jiang , Zheng-Ping Zhang , Guang-Bing Chen , Dong-Bing Fu , Yu-Xin Wang , Lei Zhang , Rong-Ke Ye , Can Zhu , Yu-Han Gao
摘要： A comparator offset voltage self-correction circuit is disclosed. A comparator offset voltage which is caused by the semiconductor process parameter randomness also has randomness. Due to the randomness of the comparator offset voltage, a reference voltage of a parallel comparator in a parallel-conversion-type analog-to-digital converter is uncertain. If the comparator offset voltage is large, the parallel-conversion-type analog-to-digital converter may even have a functional error. The comparator offset voltage self-correction circuit provided in the present invention can correct a random offset voltage of a comparator to meet requirements. Therefore, by means of the circuit and a method provided in the present invention, adverse influence of the random offset of the comparator on the function and the performance of the parallel-conversion-type analog-to-digital converter is eliminated, thereby greatly improving the speed and the performance of the analog-to-digital converter, in particular the parallel-conversion-type analog-to-digital converter.
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公开(公告)号：US10666243B2
公开(公告)日：2020-05-26
申请号：US16475123
申请日：2016-07-07
发明人： Dai-Guo Xu , Gang-Yi Hu , Ru-Zhang Li , Jian-An Wang , Guang-Bing Chen , Yu-Xin Wang , Dong-Bing Fu , Tao Liu
IPC分类号： H03K5/00 , H03K5/24 , H03K19/00 , H03K19/003
摘要： A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.
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公开(公告)号：US09966967B2
公开(公告)日：2018-05-08
申请号：US15521178
申请日：2015-05-21
发明人： Dai-Guo Xu , Shi-Liu Xu , Gang-Yi Hu , Guang-Bing Chen , Jian-An Wang
CPC分类号： H03M1/0809 , H03M1/00 , H03M1/0695 , H03M1/1023 , H03M1/12 , H03M1/144 , H03M1/204 , H03M1/282
摘要： A high-speed successive approximation analog-to-digital converter of two bits per cycle, includes three switches, two capacitor arrays, three comparators, an encoding circuit, a first switch array corresponding to the first capacitor array, a second switch array corresponding to the second capacitor array, a shifting register and a digital correction unit. The analog-to-digital converter, featuring doubled speed, realizes a successive approximation process without any fault when a high-bit large capacitor is unsettled. Thus no redundancy bit capacitor is required to compensate for unsettled pre-stage large capacitor. By using the encoding circuit, a thermometer code is converted into a binary code effectively, and inherent errors of comparators are reduced by the randomization of three comparators.
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公开(公告)号：US10735014B2
公开(公告)日：2020-08-04
申请号：US16475120
申请日：2016-06-17
发明人： Jie Pu , Gang-yi Hu , Dong-Bing Fu , Xi Chen , Xing-Fa Huang , Yu-Xin Wang , Guang-Bing Chen , Ru-Zhang Li
摘要： An error compensation correction device for a pipeline analog-to-digital converter includes a correction pipeline stage and a conventional pipeline stage. For each correction pipeline stage, a corresponding error estimation circuit, a level edge detection circuit, a random level generation circuit, and MUX circuit being provided. The present disclosure can track and correct non-ideal properties and mismatching errors in real time over time along with the change of the surroundings without interrupting the ADC normal work of the pipeline. Thus the correction value is closer to the real situation.
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公开(公告)号：US10128830B2
公开(公告)日：2018-11-13
申请号：US15318975
申请日：2014-04-17
发明人： Rong-Bin Hu , Guang-Bing Chen , Gang-Yi Hu , Yong-Lu Wang , Zheng-Ping Zhang , Can Zhu , Rong-Ke Ye , Lei Zhang , Yu-Han Gao
IPC分类号： G11C27/02 , H03K17/082
摘要： A track and hold circuit comprises an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode and a sampling capacitor. The input buffer amplifier receives an input signal. In a track phase, the sampling switch is electrically connected to an emitter electrode of the drive triode; the input signal charges the sampling capacitor after being buffered by the input buffer amplifier, amplified without distortion by the unit gain amplifier module and driven by the drive triode. In a hold phase, the sampling switch is electrically connected to a base electrode of the drive triode; the base voltage of the drive triode is pulled down until the drive triode is cut off; electrical charges on the sampling capacitor are thereby held, causing the signal to be held on the sampling capacitor.
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