公开(公告)号：US07927928B2

公开(公告)日：2011-04-19

申请号：US12014985

申请日：2008-01-16

申请人： Christophe Pierrat

发明人： Christophe Pierrat

IPC分类号： H01L21/335

CPC分类号： H01L21/0337

摘要： Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the filled pattern to remove portions of the final material beyond dimensions of the layout elements.

摘要翻译： 公开了半导体器件制造和布局生成的系统和方法。 一种示例性方法包括沉积第一材料的层并图案化该层以形成初始图案的过程，其中初始图案使用单次曝光来定义布局元件的关键特征; 在衬底上的第一图案上沉积间隔物材料并蚀刻间隔物材料，使得间隔物材料从衬底和第一图案的水平表面移除，但保持邻近第一图案的垂直表面; 在将间隔物材料留在间隔物图案中的同时从衬底去除初始图案; 用最终材料填充间隔图案; 以及修整填充图案以去除最终材料的部分超出布局元件的尺寸。

公开(公告)号：US20100251202A1

公开(公告)日：2010-09-30

申请号：US12730370

申请日：2010-03-24

申请人： Christophe Pierrat

发明人： Christophe Pierrat

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70125 ,  G03F7/70441 ,  G03F7/705

摘要： The manufacturing of integrated circuits relies on the use of lithography simulation to predict the image of the mask created on the wafer. Such predictions can be used for example to assess the quality of the images, verify the manufacturability of such images, perform using OPC necessary correction of the mask data to achieve images close to the targets, optimize the printing parameters such as the illumination source, or globally optimize the source and the mask to achieve better printability. This disclosure provides a technique based on the association of at least one kernel function per source region or source point. Each kernel function can be directly convoluted with a mask image to create a prediction of the wafer image. As the kernel functions are associated with the source, the source can be easily changed to create new models. The optical system can be fully described by computing the possible kernels for all possible source points and all possible numerical apertures. Therefore this technique is ideally suited for source-mask optimization as well as source-mask-numerical aperture optimization, and their associated applications.

摘要翻译： 集成电路的制造依赖于使用光刻模拟来预测在晶片上产生的掩模的图像。 这样的预测可以用于例如评估图像的质量，验证这些图像的可制造性，使用OPC对掩模数据进行必要的校正以实现靠近目标的图像，优化诸如照明源的打印参数，或者 全面优化源码和掩码以实现更好的可打印性。 本公开提供了一种基于每个源区域或源点至少一个核心功能的关联的技术。 每个内核函数可以直接与掩模图像卷积，以创建晶片图像的预测。 由于内核功能与源相关联，源可以轻松更改以创建新模型。 可以通过计算所有可能的源点和所有可能的数值孔径的可能的内核来完全描述光学系统。 因此，该技术非常适用于源掩码优化以及源掩码数值孔径优化及其相关应用。

公开(公告)号：US07614033B2

公开(公告)日：2009-11-03

申请号：US11442110

申请日：2006-05-26

申请人： Christophe Pierrat ,  Alfred Kwok-Kit Wong

发明人： Christophe Pierrat ,  Alfred Kwok-Kit Wong

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F1/68

摘要： The manufacturing of integrated circuits relies on the use of optical proximity correction (OPC) to correct the printing of the features on the wafer. The data is subsequently fractured to accommodate the format of existing mask writer. The complexity of the correction after OPC can create some issues for vector-scan e-beam mask writing tools as very small slivers are created when the data is converted to the mask write tool format. Moreover the number of shapes created after fracturing is quite large and are not related to some important characteristics of the layout like for example critical areas. A new technique is proposed where the order of the OPC and fracturing steps is reversed. The fracturing step is done first in order to guarantee that no slivers are created and that the number of shapes is minimized. The shapes created can also follow the edges of critical zones so that critical and non-critical edges can be differentiated during the subsequent OPC step.

摘要翻译： 集成电路的制造依赖于使用光学邻近校正（OPC）来校正晶片上的特征的打印。 数据随后被破碎以适应现有的掩码写入器的格式。 当OPC将数据转换为掩码写入工具格式时，OPC之后的校正的复杂度可能会为矢量扫描电子束掩模写入工具创建一些问题，因为非常小的条带被创建。 此外，压裂后产生的形状数量相当大，与布局的某些重要特征无关，例如关键区域。 提出了一种新技术，其中OPC和压裂步骤的顺序相反。 首先进行压裂步骤，以确保没有创建条子，并且形状的数量最小化。 所创建的形状也可以跟随关键区域的边缘，以便在随后的OPC步骤期间可以区分关键和非关键边缘。

公开(公告)号：US07585595B2

公开(公告)日：2009-09-08

申请号：US10920027

申请日：2004-08-17

申请人： Christophe Pierrat

发明人： Christophe Pierrat

IPC分类号： G03F1/00

CPC分类号： G03F1/30 ,  G03F1/36

摘要： A method extends the use of phase shift techniques to complex layouts, and includes identifying a pattern, and automatically mapping the phase shifting regions for implementation of such features. The pattern includes small features having a dimension smaller than a first particular feature size, and at least one relatively large feature, the at least one relatively large feature and another feature in the pattern having respective sides separated by a narrow space. Phase shift regions are laid out including a first set of phase shift regions to define said small features, and a second set of phase shift regions to assist definition of said side of said relatively large feature. An opaque feature is used to define the relatively large feature, and a phase shift region in the second set is a sub-resolution window inside the perimeter of the opaque feature.

摘要翻译： 一种方法将相移技术的使用扩展到复杂的布局，并且包括识别图案，并且自动映射用于实现这些特征的相移区域。 该图案包括具有小于第一特定特征尺寸的尺寸的小特征以及至少一个相对较大的特征，该图案中的至少一个相对大的特征和另一特征具有由狭窄空间分开的相应侧面。 布置相移区域，其包括第一组相移区域以限定所述小特征，以及第二组相移区域，以辅助所述相对较大特征的所述侧面的定义。 使用不透明特征来定义相对较大的特征，并且第二组中的相移区域是不透明特征的周边内的子分辨率窗口。

公开(公告)号：US07534531B2

公开(公告)日：2009-05-19

申请号：US11035788

申请日：2005-01-13

申请人： Christophe Pierrat

发明人： Christophe Pierrat

IPC分类号： G03F1/02

CPC分类号： G03F1/30 ,  G03F1/70

摘要： A full phase shifting mask (FPSM) can be advantageously used in a damascene process for hard-to-etch metal layers. Because the FPSM can be used with a positive photoresist, features on an original layout can be replaced with shifters on a FPSM layout. Adjacent shifters should be of opposite phase, e.g. 0 and 180 degrees. In one embodiment, a dark field trim mask can be used with the FPSM. The trim mask can include cuts that correspond to cuts on the FPSM. Cuts on the FPSM can be made to resolve phase conflicts between proximate shifters. In one case, exposing two proximate shifters on the FPSM and a corresponding cut on the trim mask can form a feature in the metal layer. The FPSM and/or the trim mask can include proximity corrections to further improve printing resolution.

摘要翻译： 全相移掩模（FPSM）可有利地用于难蚀刻金属层的镶嵌工艺。 因为FPSM可以与正光致抗蚀剂一起使用，原始布局上的特征可以用FPSM布局上的移位器替代。 相邻移位器应该是相反的，例如 0和180度。 在一个实施例中，暗场修剪掩模可以与FPSM一起使用。 修剪蒙版可以包括对应于FPSM上的切割的切口。 可以对FPSM进行切割以解决相邻移位器之间的相位冲突。 在一种情况下，在FPSM上曝光两个相邻的移位器并且在修剪蒙版上相应的切割可以在金属层中形成特征。 FPSM和/或修剪掩模可以包括接近校正以进一步提高打印分辨率。

公开(公告)号：US07458056B2

公开(公告)日：2008-11-25

申请号：US11350515

申请日：2006-02-09

申请人： Christophe Pierrat

发明人： Christophe Pierrat

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： Proximity effect correction has become a necessary step in the fabrication of integrated circuit in order to improve the pattern fidelity of current lithography processes. Current methodology is limited by data volume increase and correction inaccuracy due to extrapolation of the correction. The invention describes a methodology based on the interpolation of the correction between selected evaluation points of the target layout. By connecting the correction points this technique also provides a mean of reducing data volume and simplifying the mask writing, inspection and repair processes. The same methodology can be applied to layouts with non-printing assist features, where the correction of the assist features is based on the quality of the image of the main feature. For vector-scan mask write tool the segments interpolating the corrections can be fractured in segments with suitable angles.

摘要翻译： 接近效应校正已经成为制造集成电路的必要步骤，以提高当前光刻工艺的图案保真度。 当前的方法受限于数据量的增加和校正误差由于外推的校正。 本发明描述了基于目标布局的所选择的评估点之间的校正的内插的方法。 通过连接校正点，该技术还提供了减少数据量并简化掩模写入，检查和修复过程的平均值。 相同的方法可以应用于具有非打印辅助特征的布局，其中辅助特征的校正基于主要特征的图像的质量。 对于矢量扫描掩模写入工具，内插校正的段可以以适当的角度在段中断裂。

公开(公告)号：US20080076042A1

公开(公告)日：2008-03-27

申请号：US11926648

申请日：2007-10-29

申请人： Michel Cote ,  Christophe Pierrat

发明人： Michel Cote ,  Christophe Pierrat

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G03F7/70466 ,  G03F1/26 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/70558

摘要： A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

摘要翻译： 描述了一种用于定义用于在集成电路中定义材料层的全相布局的方法。 该方法可用于定义，排列和细化移相器以基本上使用相移限定层。 通过该过程，产生交替光圈，暗场相移掩模和互补掩模的计算机可读定义。 掩模可以由定义制成，然后用于在集成电路中制造一层材料。 移相器或切口之间的分离被设计为便于掩模制造，同时还使由相移掩模限定的每个特征的量最大化。 成本函数用于描述相位分配的相对质量，并选择较高质量的相位分配并减少相位冲突。

公开(公告)号：US07155689B2

公开(公告)日：2006-12-26

申请号：US10680592

申请日：2003-10-07

申请人： Christophe Pierrat ,  Alfred K. Wong

发明人： Christophe Pierrat ,  Alfred K. Wong

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5036 ,  G06F17/5068

摘要： Subtleties of advanced fabrication processes and nano-scale phenomena associated with integrated circuit miniaturization have exposed the insufficiencies of design rules. Such inadequacies have adverse impact on all parts of the integrated circuit creation flow where design rules are used. In addition, segregation of the various layout data modification steps required for deep sub-micrometer manufacturing are resulting in slack and inefficiencies. This invention describes methods to improve integrated circuit creation via the use of a unified model of fabrication processes and circuit elements that can complement or replace design rules. By capturing the interdependence among fabrication processes and circuit elements, the unified model enables efficient layout generation, resulting in better integrated circuits.

摘要翻译： 与集成电路小型化相关的先进制造工艺和纳米尺度现象的小说暴露了设计规则的不足之处。 这种不足之处对于使用设计规则的集成电路创建流程的所有部分都有不利影响。 另外，深度亚微米制造所需的各种布局数据修改步骤的分离导致松弛和低效率。 本发明描述了通过使用可以补充或替代设计规则的制造过程和电路元件的统一模型来改进集成电路创建的方法。 通过捕获制造工艺和电路元件之间的相互依赖性，统一模型可实现有效的布局生成，从而形成更好的集成电路。

公开(公告)号：US07055127B2

公开(公告)日：2006-05-30

申请号：US10694474

申请日：2003-10-27

申请人： Christophe Pierrat ,  Alfred K. Wong

发明人： Christophe Pierrat ,  Alfred K. Wong

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F1/68

摘要： The manufacturing of integrated circuits relies on the use of optical proximity correction (OPC) to correct the printing of the features on the wafer. The data is subsequently fractured to accommodate the format of existing mask writer. The complexity of the correction after OPC can create some issues for vector-scan e-beam mask writing tools as very small slivers are created when the data is converted to the mask write tool format. Moreover the number of shapes created after fracturing is quite large and are not related to some important characteristics of the layout like for example critical areas. A new technique is proposed where the order of the OPC and fracturing steps is reversed. The fracturing step is done first in order to guarantee that no slivers are created and that the number of shapes is minimized. The shapes created can also follow the edges of critical zones so that critical and non-critical edges can be differentiated during the subsequent OPC step.

公开(公告)号：US07010764B2

公开(公告)日：2006-03-07

申请号：US10413052

申请日：2003-04-14

申请人： Christophe Pierrat

发明人： Christophe Pierrat

IPC分类号： G06F17/50 ,  G03F1/00 ,  G03C5/00

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： Proximity effect correction has become a necessary step in the fabrication of integrated circuit in order to improve the pattern fidelity of current lithography processes. Current methodology is limited by data volume increase and correction inaccuracy due to extrapolation of the correction. The invention describes a methodology based on the interpolation of the correction between selected evaluation points of the target layout. By connecting the correction points this technique also provides a mean of reducing data volume and simplifying the mask writing, inspection and repair processes. The same methodology can be applied to layouts with non-printing assist features, where the correction of the assist features is based on the quality of the image of the main feature. For vector-scan mask write tool the segments interpolating the corrections can be fractured in segments with suitable angles.