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252 条记录 (耗时 0.056 秒)

    Method and data storage device for laser free heat-assisted magnetic recording
    12.
    发明授权
    Method and data storage device for laser free heat-assisted magnetic recording 有权
    无激光热辅助磁记录方法和数据存储装置

    公开(公告)号：US08792211B2

    公开(公告)日：2014-07-29

    申请号：US13977639

    申请日：2010-12-31

    申请人： Zhimin Yuan ,  Bo Liu ,  Boon Hao Low ,  Tiejun Zhou ,  Siang Huei Leong ,  Mingsheng Zhang

    发明人： Zhimin Yuan ,  Bo Liu ,  Boon Hao Low ,  Tiejun Zhou ,  Siang Huei Leong ,  Mingsheng Zhang

    IPC分类号： G11B5/127

    CPC分类号： G11B5/127 ,  G11B5/314 ,  G11B2005/0021

    摘要： A data storage device with a heat assisted magnetic recording (HAMR) system, a magnetic recording medium, and method for data storage are provided. The data storage device includes a magnetic recording medium, a magnetic recording head, a power supply, a controller and a switching device. The magnetic recording head includes a main pole having a surface area facing the magnetic recording medium. The controller is coupled to the magnetic recording head for controlling writing information to and reading information from the magnetic recording medium. The switching device electrically couples the power supply between the main pole and the magnetic recording medium in response to a signal provided from the controller when writing information to the magnetic recording medium. The magnetic recording medium comprises a plurality of layers, including a heating layer, a field enhanced conduction layer, and an electrode layer. The electrode layer is electrically coupleable to the power supply and the magnetic recording head for heating a portion of the heating layer opposite the magnetic recording head during writing of data by the magnetic recording head to the magnetic recording medium, the portion of the heating layer defined by an electric field applied to the field enhanced conduction layer.

    摘要翻译： 提供具有热辅助磁记录（HAMR）系统，磁记录介质和数据存储方法的数据存储装置。 数据存储装置包括磁记录介质，磁记录头，电源，控制器和开关装置。 磁记录头包括具有面向磁记录介质的表面积的主极。 控制器耦合到磁记录头，用于控制向磁记录介质写入信息和从磁记录介质读取信息。 当将信息写入磁记录介质时，开关装置响应于从控制器提供的信号，在主极和磁记录介质之间电耦合电源。 磁记录介质包括多个层，包括加热层，场增强传导层和电极层。 所述电极层电耦合到所述电源和所述磁记录头，用于在由所述磁记录头向所述磁记录介质写入数据期间加热与所述磁记录头相对的所述加热层的一部分，所述加热层的所述部分被限定 通过施加到场增强导电层的电场。

    Column redundancy circuitry for non-volatile memory
    14.
    发明授权
    Column redundancy circuitry for non-volatile memory 有权
    用于非易失性存储器的列冗余电路

    公开(公告)号：US08681548B2

    公开(公告)日：2014-03-25

    申请号：US13463422

    申请日：2012-05-03

    申请人： Bo Liu ,  Frank Wanfang Tsai ,  Jongmin Park ,  Yan Li

    发明人： Bo Liu ,  Frank Wanfang Tsai ,  Jongmin Park ,  Yan Li

    IPC分类号： G11C16/06 ,  G11C8/00 ,  G11C8/18

    CPC分类号： G11C29/848 ,  G11C7/1036 ,  G11C8/04 ,  G11C29/78

    摘要： In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to consecutive logical address will be distributed into different physical locations. For example, all column data can be physically grouped into, say, 5 divisions and user data can be written into or accessed from one division after another consecutively. Each division has its own clock control. The column redundancy block can generate bad column locations' information and send it to control logic to switch the user clock to a different division clock, thereby skipping bad columns. By controlling the clocks for different columns, the user can directly access good columns without touching bad columns.

    摘要翻译： 在非易失性存储器电路中，呈现技术，使得在存储器数据输入和输出操作期间可以忽略和/或替换坏列。 用于此目的的列冗余电路可减少电路尺寸并提高性能。 用户数据以交错方式分组，使得属于连续逻辑地址的数据将被分配到不同的物理位置。 例如，所有列数据可以被物理地分组成5个部分，并且用户数据可以被连续地从一个部门写入或访问。 每个部门都有自己的时钟控制。 列冗余块可以产生错误的列位置信息，并将其发送到控制逻辑，以将用户时钟切换到不同的分频时钟，从而跳过不良列。 通过控制不同列的时钟，用户可以直接访问好的列，而不会碰坏列。

    Microbial production of fatty alcohols
    15.
    发明授权
    Microbial production of fatty alcohols 有权
    微生物生产脂肪醇

    公开(公告)号：US08633002B2

    公开(公告)日：2014-01-21

    申请号：US12854848

    申请日：2010-08-11

    申请人： Paul G. Roessler ,  Kevin Watts ,  Bo Liu

    发明人： Paul G. Roessler ,  Kevin Watts ,  Bo Liu

    IPC分类号： C12P7/02 ,  C12P7/00

    CPC分类号： C12P7/04 ,  C12N9/0008 ,  C12N9/001

    摘要： Genes and strains of recombinant microorganisms are provided that are engineered to produce fatty alcohols and fatty alcohol derivatives. The organisms can include one, two, three or more transgenes that direct the biosynthesis of one or more fatty alcohols or derivatives. Methods of producing fatty alcohols using transgenic microorganisms are also provided.

    摘要翻译： 提供重组微生物的基因和菌株，其被工程化以产生脂肪醇和脂肪醇衍生物。 生物体可以包括一种，两种，三种或更多种转导子，其指导一种或多种脂肪醇或衍生物的生物合成。 还提供了使用转基因微生物生产脂肪醇的方法。

    Audio jack connector
    16.
    发明授权
    Audio jack connector 失效
    音频插孔连接器

    公开(公告)号：US08616922B2

    公开(公告)日：2013-12-31

    申请号：US13405232

    申请日：2012-02-24

    申请人： Bo Liu ,  Rui-Bo Zhan

    发明人： Bo Liu ,  Rui-Bo Zhan

    IPC分类号： H01R24/04

    CPC分类号： H01R12/57 ,  H01R24/58

    摘要： An audio jack connector adapted for soldering on a circuit board and engaging with an audio plug connector includes an insulating housing and a plurality of terminals. The insulating housing has a main body, and an insertion portion connecting with one side of the main body. The insertion portion defines an insertion hole for receiving the audio plug connector therein. The main body defines a plurality of terminal grooves with bottoms thereof passing through a bottom surface of the main body. The insulating housing defines a plurality of mouths communicating between the insertion hole and the terminal grooves. The terminals are disposed in the terminal grooves. Each terminal has a contact portion projecting into the insertion hole through the mouth to electrically contact with the audio plug connector, and a soldering portion received in the bottom of the terminal groove to be soldered on the circuit board.

    摘要翻译： 适于焊接在电路板上并与音频插头连接件相配合的音频插孔连接器包括绝缘壳体和多个端子。 绝缘壳体具有主体和与主体的一侧连接的插入部。 插入部分限定用于在其中接收音频插头连接器的插入孔。 主体限定多个端子槽，其底部通过主体的底面。 绝缘壳体限定了在插入孔和端子槽之间连通的多个口。 端子设置在端子槽中。 每个端子具有通过口突出到插入孔中的接触部分，以与音频插头连接器电接触，以及接收在待焊接在电路板上的端子槽的底部的焊接部分。

    Column Redundancy Circuitry for Non-Volatile Memory
    18.
    发明申请
    Column Redundancy Circuitry for Non-Volatile Memory 有权
    非易失性存储器的列冗余电路

    公开(公告)号：US20130294162A1

    公开(公告)日：2013-11-07

    申请号：US13463422

    申请日：2012-05-03

    申请人： Bo Liu ,  Frank Wanfang Tsai ,  Jongmin Park ,  Yan Li

    发明人： Bo Liu ,  Frank Wanfang Tsai ,  Jongmin Park ,  Yan Li

    IPC分类号： G11C16/06

    CPC分类号： G11C29/848 ,  G11C7/1036 ,  G11C8/04 ,  G11C29/78

    摘要： In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to consecutive logical address will be distributed into different physical locations. For example, all column data can be physically grouped into, say, 5 divisions and user data can be written into or accessed from one division after another consecutively. Each division has its own clock control. The column redundancy block can generate bad column locations' information and send it to control logic to switch the user clock to a different division clock, thereby skipping bad columns. By controlling the clocks for different columns, the user can directly access good columns without touching bad columns.

    摘要翻译： 在非易失性存储器电路中，呈现技术，使得在存储器数据输入和输出操作期间可以忽略和/或替换坏列。 用于此目的的列冗余电路可减少电路尺寸并提高性能。 用户数据以交错方式分组，使得属于连续逻辑地址的数据将被分配到不同的物理位置。 例如，所有列数据可以被物理地分组成5个部分，并且用户数据可以被连续地从一个部门写入或访问。 每个部门都有自己的时钟控制。 列冗余块可以产生错误的列位置信息，并将其发送到控制逻辑，以将用户时钟切换到不同的分频时钟，从而跳过不良列。 通过控制不同列的时钟，用户可以直接访问好的列，而不会碰坏列。

    METHOD OF FABRICATING DUAL TRENCH ISOLATED EPITAXIAL DIODE ARRAY
    20.
    发明申请
    METHOD OF FABRICATING DUAL TRENCH ISOLATED EPITAXIAL DIODE ARRAY 有权
    双层分离分离的外延二极体阵列的方法

    公开(公告)号：US20130189799A1

    公开(公告)日：2013-07-25

    申请号：US13203135

    申请日：2011-06-23

    申请人： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

    发明人： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76205 ,  H01L21/76224 ,  H01L27/0814

    摘要： The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches. This invention can be used for diode-driven, high-density, large-capacity memory, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory; the method thereof is completely compatible with conventional complementary metal-oxide semiconductor (CMOS) process, and because the diode arrays can be formed before the formation of peripheral circuits, no drift of peripheral circuits will be caused by the thermal process thereof, thereby solving the technical challenge of fabricating high-density, large-capacity embedded phase change random access memory.

    摘要翻译： 本发明公开了一种制造双沟槽隔离外延二极管阵列的方法。 该方法开始于在衬底上形成重掺杂的第一导电类型区域和重掺杂的第二导电类型区域，随后进行外延生长，然后通过深沟槽蚀刻形成二极管阵列字线之间的隔离，并形成 通过浅沟槽蚀刻垂直于深沟槽的位线之间的隔离，最后通过离子注入由深和浅沟槽隔离所包围的区域中形成分离的二极管阵列单元。 本发明还提供了一种防止由前述的双浅沟槽隔离的外延二极管阵列的相邻字线和位线之间的串扰电流的方法。 本发明可用于二极管驱动，高密度，大容量存储器，如相变随机存取存储器，电阻存储器，磁存储器和铁电存储器; 其方法与常规的互补金属氧化物半导体（CMOS）工艺完全兼容，并且由于可以在外围电路形成之前形成二极管阵列，所以不会由于其热处理而引起外围电路的漂移，从而解决了 制造高密度，大容量嵌入式相变随机存取存储器的技术挑战。