公开(公告)号：US06872581B2

公开(公告)日：2005-03-29

申请号：US10123842

申请日：2002-04-15

Applicant: Christopher Shaw ,  Chun-Cheng Tsao ,  Theodore R. Lundquist

Inventor： Christopher Shaw ,  Chun-Cheng Tsao ,  Theodore R. Lundquist

IPC: G01R31/302 ,  G01R31/311 ,  H01L21/66 ,  H01L21/00

CPC classification number: G01R31/311 ,  H01L22/14 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Methods for integrated circuit diagnosis, characterization or modification using a charged particle beam. In one implementation, the bulk silicon substrate of an integrated circuit is thinned to about 1 to 3 μm from the deepest well, a voltage is applied to a circuit element that is beneath the outer surface of the thinned substrate. The applied voltage induces an electrical potential on the outer surface, which is detected as a surface feature on the outer surface by its interaction with the charged particle beam.

Abstract translation: 使用带电粒子束进行集成电路诊断，表征或修改的方法。 在一个实施方案中，将集成电路的体硅衬底从最深的孔减薄到约1至3μm，将电压施加到在薄化衬底的外表面下方的电路元件。 所施加的电压在外表面上引起电位，其通过与带电粒子束的相互作用被检测为外表面上的表面特征。

公开(公告)号：US08173948B2

公开(公告)日：2012-05-08

申请号：US12582553

申请日：2009-10-20

Applicant: Chun-Cheng Tsao

Inventor： Chun-Cheng Tsao

IPC: G01J1/42

CPC classification number: H01J37/3056 ,  H01J37/228 ,  H01J2237/2482 ,  H01J2237/31749 ,  H01L21/76892 ,  H01L21/76898

Abstract: An optical coupling apparatus for a dual column charged particle beam tool allowing both optical imaging of an area of an integrated circuit, as well as localized heating of the integrated circuit to form silicide. In one embodiment, optical paths from a whitelight source and a laser source are coupled together by way of first and second beam splitters so that a single optical port of the dual column tool may be utilized for both imaging and heating. In another embodiment, a single laser source is employed to provide both illumination for standard microscopy-type imaging, as well as localized heating. In a third embodiment, a single laser source provides heating along with localized illumination for confocal scanning microscopy-type imaging.

Abstract translation: 一种用于双列带电粒子束工具的光耦合装置，其允许集成电路的区域的光学成像，以及集成电路的局部加热以形成硅化物。 在一个实施例中，来自白光源和激光源的光路通过第一和第二分束器耦合在一起，使得双列工具的单个光学端口可以用于成像和加热。 在另一个实施例中，使用单个激光源来为标准显微镜型成像以及局部加热提供照明。 在第三实施例中，单个激光源与局部照明一起提供加热以用于共焦扫描显微镜型成像。

公开(公告)号：US07612321B2

公开(公告)日：2009-11-03

申请号：US11222932

申请日：2005-09-08

Applicant: Chun-Cheng Tsao

Inventor： Chun-Cheng Tsao

IPC: G01J1/42

CPC classification number: H01J37/3056 ,  H01J37/228 ,  H01J2237/2482 ,  H01J2237/31749 ,  H01L21/76892 ,  H01L21/76898

Abstract: An optical coupling apparatus for a dual column charged particle beam tool allowing both optical imaging of an area of an integrated circuit, as well as localized heating of the integrated circuit to form silicide. In one embodiment, optical paths from a whitelight source and a laser source are coupled together by way of first and second beam splitters so that a single optical port of the dual column tool may be utilized for both imaging and heating. In another embodiment, a single laser source is employed to provide both illumination for standard microscopy-type imaging, as well as localized heating. In a third embodiment, a single laser source provides heating along with localized illumination for confocal scanning microscopy-type imaging.

Abstract translation: 一种用于双列带电粒子束工具的光耦合装置，其允许集成电路的区域的光学成像，以及集成电路的局部加热以形成硅化物。 在一个实施例中，来自白光源和激光源的光路通过第一和第二分束器耦合在一起，使得双列工具的单个光学端口可以用于成像和加热。 在另一个实施例中，使用单个激光源来为标准显微镜型成像以及局部加热提供照明。 在第三实施例中，单个激光源与局部照明一起提供加热以用于共焦扫描显微镜型成像。

公开(公告)号：US20070293052A1

公开(公告)日：2007-12-20

申请号：US11754466

申请日：2007-05-29

Applicant: Erwan Le Roy ,  Chun-Cheng Tsao ,  Theodore Lundquist ,  Rajesh Jain

Inventor： Erwan Le Roy ,  Chun-Cheng Tsao ,  Theodore Lundquist ,  Rajesh Jain

IPC: H01L21/302

CPC classification number: H01L21/3065 ,  H01J37/228 ,  H01J37/3056 ,  H01J2237/2482 ,  H01J2237/30466 ,  H01J2237/31749 ,  H01L22/12 ,  H01L22/26

Abstract: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection and/or characteristics of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Resulting fringes will be a function, in part, of the thickness and/or profile of the trench floor. Milling may be controlled as a function of the detected fringe patterns.

Abstract translation: 一种使用光学干涉条纹处理集成电路的装置和方法。 在处理期间，一个或多个波长的光被引导到集成电路上，并且基于干涉条纹和其特性的检测，可以控制进一步的处理。 一种实施方案涉及集成电路的带电粒子束处理，作为干涉条纹的检测和/或特征的函数。 在集成电路的衬底中或其上执行带电粒子束沟槽铣削操作。 光线指向沟槽的地板。 干涉条纹可以由从地板反射的光与来自电路结构的光之间的建构性或破坏性干扰形成。 所产生的条纹将部分地是沟槽地板的厚度和/或轮廓的函数。 作为检测到的条纹图案的函数可以控制铣削。

公开(公告)号：US20060188797A1

公开(公告)日：2006-08-24

申请号：US11362240

申请日：2006-02-24

Applicant: Erwan Roy ,  Chun-Cheng Tsao ,  Theodore Lundquist

Inventor： Erwan Roy ,  Chun-Cheng Tsao ,  Theodore Lundquist

IPC: G03C5/00 ,  A61N5/00 ,  G21G5/00

CPC classification number: H01J37/3174 ,  B23K26/03 ,  B23K26/032 ,  B82Y10/00 ,  B82Y40/00

Abstract: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, light is directed on the integrated circuit and based upon the detection of interference fringes, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. When the floor approaches the underlying circuit structures, some light is reflected from the floor of the trench and some light penetrates the substrate and is reflected off the underlying circuit structures. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Processing may be controlled as function of the detection of interference fringes.

Abstract translation: 一种使用光学干涉条纹处理集成电路的装置和方法。 在处理期间，光被引导到集成电路上，并且基于干涉条纹的检测，可以控制进一步的处理。 一种实施方案涉及集成电路的带电粒子束处理作为干涉条纹检测的功能。 在集成电路的衬底中或其上执行带电粒子束沟槽铣削操作。 光照在沟槽的地板上。 当地板接近下面的电路结构时，一些光从沟槽的底部反射，并且一些光穿透衬底并从下面的电路结构反射。 干涉条纹可以由从地板反射的光与来自电路结构的光之间的建构性或破坏性干扰形成。 作为检测干涉条纹的功能，可以控制处理。

公开(公告)号：US20050236583A1

公开(公告)日：2005-10-27

申请号：US11109545

申请日：2005-04-19

Applicant: Erwan Roy ,  Chun-Cheng Tsao

Inventor： Erwan Roy ,  Chun-Cheng Tsao

IPC: H01J37/30 ,  H01J37/305 ,  H01L21/3065 ,  A61N5/00 ,  G21G5/00

CPC classification number: H01J37/3005 ,  H01J37/3056 ,  H01J2237/30466 ,  H01L21/3065

Abstract: Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using a FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The process includes a precise optical endpointing technique to monitor the remaining thickness of the semiconductor substrate at the floor of the trench. It is important to terminate etching of the trench so that the trench floor extends as close to the active semiconductor structures as desired and yet is not detrimental to device operation. This is done without introducing a need for any additional tool. This is carried out using an infra-red optical technique which observes the interference fringes generated by the reflections from the silicon substrate surface and from semiconductor device circuitry layers to quantify the remaining semiconductor substrate thickness in the trench.

Abstract translation: 用于从集成电路衬底的背面暴露诸如金属化层的选定部分的集成电路器件的选定特征的装置和方法，而不干扰诸如有源半导体区域的器件的相邻特征。 这是使用FIB（聚焦离子束）蚀刻工艺结合光学显微镜的观察来进行的，以通过衬底形成沟槽。 该方法包括精确的光学终点技术，以监测沟槽底部的半导体衬底的剩余厚度。 重要的是终止沟槽的蚀刻，使得沟槽底板根据需要延伸到接近有源半导体结构，并且不会对器件操作产生不利影响。 这不需要任何额外的工具就可以完成。 这使用红外光学技术进行，该技术观察由硅衬底表面和半导体器件电路层的反射产生的干涉条纹，以量化沟槽中剩余的半导体衬底厚度。

公开(公告)号：US06939209B2

公开(公告)日：2005-09-06

申请号：US10693310

申请日：2003-10-24

Applicant: Chun-Cheng Tsao ,  John Valliant

Inventor： Chun-Cheng Tsao ,  John Valliant

IPC: B24B1/00 ,  B24B7/22 ,  B24B37/04 ,  B24B49/12

CPC classification number: B24B49/12 ,  B24B7/228 ,  B24B37/042

Abstract: A reliable, inexpensive “back side” thinning process and apparatus therefor, capable of globally thinning an integrated circuit die to a target thickness of 10 microns, and maintaining a yield of at least 80%, for chip repair and/or failure analysis of the packaged die. The flip-chip packaged die is exposed at its backside and mounted on a lapping machine with the backside exposed. The thickness of the die is measured at at least five locations on the die. The lapping machine grinds the exposed surface of the die to a thickness somewhat greater than the target thickness. The exposed surface of the die is polished. The thickness of the die is again measured optically with high accuracy. Based on the thickness data collected, appropriate machine operating parameters for further grinding and polishing of the exposed surface are determined. Further grinding and polishing are performed. These steps are repeated until the target thickness is reached.

Abstract translation: 一种可靠，廉价的“背面”稀释方法及其设备，能够将集成电路管芯全局变薄至目标厚度为10微米，并保持至少80％的产量，用于芯片修复和/或故障分析 包装模具 倒装芯片封装的裸片在其背面露出并安装在背面暴露的研磨机上。 模具的厚度在模具上的至少五个位置处被测量。 研磨机将模具的暴露表面研磨到稍大于目标厚度的厚度。 模具的暴露表面被抛光。 再次以高精度光学测量模具的厚度。 基于收集的厚度数据，确定用于进一步研磨和抛光暴露表面的合适的机器操作参数。 进行进一步研磨和抛光。 重复这些步骤，直到达到目标厚度。

公开(公告)号：US06252222B1

公开(公告)日：2001-06-26

申请号：US09483463

申请日：2000-01-13

Applicant: Steven A. Kasapi ,  Chun-Cheng Tsao ,  Seema Somani

Inventor： Steven A. Kasapi ,  Chun-Cheng Tsao ,  Seema Somani

IPC: G01R31265

CPC classification number: G01R31/308

Abstract: A laser beam is used to probe an integrated circuit device under test. A single laser provides a single laser pulse which is divided into two pulses, both of which are incident upon the device under test. After the two pulses interact with the device under test, the two pulses are separated and detected by two photo detectors. The electrical signals output by the photo detectors are then subtracted, which cancels out any common mode noise induced on both pulses including noise due to mechanical vibration of the device under test and also any noise from the laser. The difference signal can be used to reproduce a time varying signal in the device under test.

Abstract translation: 激光束用于探测被测集成电路器件。 单个激光器提供单个激光脉冲，其被分成两个脉冲，两个脉冲都入射在被测器件上。 在两个脉冲与被测器件相互作用之后，两个脉冲被两个光电检测器分离并检测。 然后减去由光电检测器输出的电信号，这消除了由于被测器件的机械振动引起的包括噪声在内的两种脉冲引起的任何共模噪声，以及来自激光器的任何噪声。 差分信号可用于在被测器件中再现时变信号。