公开(公告)号：US07245133B2

公开(公告)日：2007-07-17

申请号：US10985808

申请日：2004-11-09

Applicant: Chun-Cheng Tsao ,  Eugene Delenia

Inventor： Chun-Cheng Tsao ,  Eugene Delenia

IPC: G01R31/302 ,  G01L21/30

CPC classification number: G01R31/302

Abstract: An integrated FIB/PEM apparatus and method for performing failure analysis on integrated circuits. In-situ failure analysis is enabled by integrating Photon Emission Microscopy into a Focused Ion Beam system, thereby improving throughput and efficiency of Failure Analysis. An iterative method is described for identifying and localizing fault sites on the circuit.

Abstract translation: 用于对集成电路执行故障分析的集成FIB / PEM装置和方法。 通过将光子发射显微镜集成到聚焦离子束系统中来实现原位故障分析，从而提高故障分析的吞吐量和效率。 描述了用于识别和定位电路上的故障位置的迭代方法。

公开(公告)号：US06672947B2

公开(公告)日：2004-01-06

申请号：US09924736

申请日：2001-08-07

Applicant: Chun-Cheng Tsao ,  John Valliant

Inventor： Chun-Cheng Tsao ,  John Valliant

IPC: B24B100

CPC classification number: B24B49/12 ,  B24B7/228 ,  B24B37/042

Abstract: A reliable, inexpensive “back side” thinning process, capable of globally thinning an integrated circuit die to a target thickness of 10 microns, and maintaining a yield of at least 80%, for chip repair and/or failure analysis of the packaged die. The flip-chip packaged die is exposed at its backside and mounted on a lapping machine with the backside exposed. The thickness of the die is measured at at least five locations on the die. The lapping machine grinds the exposed surface of the die to a thickness somewhat greater than the target thickness. The exposed surface of the die is polished. The thickness of the die is again measured optically with high accuracy. Based on the thickness data collected, appropriate machine operating parameters for further grinding and polishing of the exposed surface are determined. Further grinding and polishing are performed. These steps are repeated until the target thickness is reached.

Abstract translation: 一种可靠，廉价的“背面”稀释工艺，能够将集成电路裸片全局变薄至目标厚度为10微米，并保持至少80％的产量，用于封装芯片的芯片修复和/或故障分析。 倒装芯片封装的裸片在其背面露出并安装在背面暴露的研磨机上。 模具的厚度在模具上的至少五个位置处被测量。 研磨机将模具的暴露表面研磨到稍大于目标厚度的厚度。 模具的暴露表面被抛光。 再次以高精度光学测量模具的厚度。 基于收集的厚度数据，确定用于进一步研磨和抛光暴露表面的合适的机器操作参数。 进行进一步研磨和抛光。 重复这些步骤，直到达到目标厚度。

公开(公告)号：US07036109B1

公开(公告)日：2006-04-25

申请号：US10274431

申请日：2002-10-17

Applicant: Chun-Cheng Tsao ,  Theodore R. Lundquist ,  William Thompson ,  Erwan Le Roy ,  Eugene A. Delenia

Inventor： Chun-Cheng Tsao ,  Theodore R. Lundquist ,  William Thompson ,  Erwan Le Roy ,  Eugene A. Delenia

IPC: G06F17/50

CPC classification number: H01J37/3056 ,  H01J2237/3174

Abstract: Methods and apparatus for integrated circuit diagnosis, characterization or modification using a focused ion beam. A method for editing an integrated circuit includes acquiring an image of structures of an integrated circuit by applying a focused ion beam to an outer surface of the integrated circuit to visualize structures beneath the outer surface of the integrated circuit. The method includes using the image to find a location of a circuit element in the integrated circuit and then performing one or more editing operations on the circuit element by applying a focused ion beam to the location found.

Abstract translation: 使用聚焦离子束进行集成电路诊断，表征或修改的方法和装置。 一种用于编辑集成电路的方法包括通过将集中的离子束施加到集成电路的外表面来获取集成电路的结构图像，以便可视化集成电路外表面下方的结构。 该方法包括使用图像来找到集成电路中的电路元件的位置，然后通过将聚焦离子束施加到所找到的位置来对电路元件执行一个或多个编辑操作。

公开(公告)号：US20060079086A1

公开(公告)日：2006-04-13

申请号：US10964157

申请日：2004-10-12

Applicant: Christian Boit ,  Theodore Lundquist ,  Chun-Cheng Tsao ,  Uwe Kerst ,  Stephan Schoemann ,  Peter Sadewater

Inventor： Christian Boit ,  Theodore Lundquist ,  Chun-Cheng Tsao ,  Uwe Kerst ,  Stephan Schoemann ,  Peter Sadewater

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: H01J37/228 ,  H01J37/3056 ,  H01J2237/2482 ,  H01J2237/31749 ,  H01L21/76892 ,  H01L21/76898

Abstract: Localized trenches or access holes are milled in a semiconductor substrate to define access points to structures of an integrated circuit intended for circuit editing. A conductor is deposited, such as with a focused ion beam tool, in the access holes and a localized heat is applied to the conductor for silicide formation, especially at the boundary between a semiconductor structure, such as diffusion regions, and the deposited conductor. Localized heat may be generated at the target location through precise laser application, current generation through the target location, or a combination thereof.

Abstract translation: 在半导体衬底中研磨局部沟槽或接入孔以限定用于电路编辑的集成电路的结构的接入点。 导电体如聚焦离子束工具沉积在入口孔中，并且局部热被施加到用于硅化物形成的导体上，特别是在诸如扩散区域的半导体结构与沉积导体之间的边界处。 可以通过精确的激光施加，通过目标位置的电流产生或其组合在目标位置产生局部化的热量。

公开(公告)号：US20060012385A1

公开(公告)日：2006-01-19

申请号：US10985808

申请日：2004-11-09

Applicant: Chun-Cheng Tsao ,  Eugene Delenia

Inventor： Chun-Cheng Tsao ,  Eugene Delenia

IPC: G01R31/302

CPC classification number: G01R31/302

Abstract: An integrated FIB/PEM apparatus and method for performing failure analysis on integrated circuits. In-situ failure analysis is enabled by integrating Photon Emission Microscopy into a Focused Ion Beam system, thereby improving throughput and efficiency of Failure Analysis. An iterative method is described for identifying and localizing fault sites on the circuit.

Abstract translation: 用于对集成电路执行故障分析的集成FIB / PEM装置和方法。 通过将光子发射显微镜集成到聚焦离子束系统中来实现原位故障分析，从而提高故障分析的吞吐量和效率。 描述了用于识别和定位电路上的故障位置的迭代方法。

公开(公告)号：US07884024B2

公开(公告)日：2011-02-08

申请号：US11754466

申请日：2007-05-29

Applicant: Erwan Le Roy ,  Chun-Cheng Tsao ,  Theodore R. Lundquist ,  Rajesh Kumar Jain

Inventor： Erwan Le Roy ,  Chun-Cheng Tsao ,  Theodore R. Lundquist ,  Rajesh Kumar Jain

IPC: H01L21/302

CPC classification number: H01L21/3065 ,  H01J37/228 ,  H01J37/3056 ,  H01J2237/2482 ,  H01J2237/30466 ,  H01J2237/31749 ,  H01L22/12 ,  H01L22/26

Abstract: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection and/or characteristics of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Resulting fringes will be a function, in part, of the thickness and/or profile of the trench floor. Milling may be controlled as a function of the detected fringe patterns.

Abstract translation: 一种使用光学干涉条纹处理集成电路的装置和方法。 在处理期间，一个或多个波长的光被引导到集成电路上，并且基于干涉条纹和其特性的检测，可以控制进一步的处理。 一种实施方案涉及集成电路的带电粒子束处理，作为干涉条纹的检测和/或特征的函数。 在集成电路的衬底中或其上执行带电粒子束沟槽铣削操作。 光线指向沟槽的地板。 干涉条纹可以由从地板反射的光与来自电路结构的光之间的建构性或破坏性干扰形成。 所产生的条纹将部分地是沟槽地板的厚度和/或轮廓的函数。 作为检测到的条纹图案的函数可以控制铣削。

公开(公告)号：US07697146B2

公开(公告)日：2010-04-13

申请号：US11362240

申请日：2006-02-24

Applicant: Erwan Le Roy ,  Chun-Cheng Tsao ,  Theodore R. Lundquist

Inventor： Erwan Le Roy ,  Chun-Cheng Tsao ,  Theodore R. Lundquist

IPC: G01B11/02

CPC classification number: H01J37/3174 ,  B23K26/03 ,  B23K26/032 ,  B82Y10/00 ,  B82Y40/00

Abstract: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, light is directed on the integrated circuit and based upon the detection of interference fringes, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. When the floor approaches the underlying circuit structures, some light is reflected from the floor of the trench and some light penetrates the substrate and is reflected off the underlying circuit structures. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Processing may be controlled as function of the detection of interference fringes.

Abstract translation: 一种使用光学干涉条纹处理集成电路的装置和方法。 在处理期间，光被引导到集成电路上，并且基于干涉条纹的检测，可以控制进一步的处理。 一种实施方案涉及集成电路的带电粒子束处理作为干涉条纹检测的功能。 在集成电路的衬底中或其上执行带电粒子束沟槽铣削操作。 光照在沟槽的地板上。 当地板接近下面的电路结构时，一些光从沟槽的底部反射，并且一些光穿透衬底并从下面的电路结构反射。 干涉条纹可以由从地板反射的光与来自电路结构的光之间的建构性或破坏性干扰形成。 作为检测干涉条纹的功能，可以控制处理。

公开(公告)号：US07439168B2

公开(公告)日：2008-10-21

申请号：US10964157

申请日：2004-10-12

Applicant: Christian Boit ,  Theodore R. Lundquist ,  Chun-Cheng Tsao ,  Uwe Jürgen Kerst ,  Stephan Schoemann ,  Peter Sadewater

Inventor： Christian Boit ,  Theodore R. Lundquist ,  Chun-Cheng Tsao ,  Uwe Jürgen Kerst ,  Stephan Schoemann ,  Peter Sadewater

IPC: H01L21/4763 ,  H01L21/3205

CPC classification number: H01J37/228 ,  H01J37/3056 ,  H01J2237/2482 ,  H01J2237/31749 ,  H01L21/76892 ,  H01L21/76898

Abstract: Localized trenches or access holes are milled in a semiconductor substrate to define access points to structures of an integrated circuit intended for circuit editing. A conductor is deposited, such as with a focused ion beam tool, in the access holes and a localized heat is applied to the conductor for silicide formation, especially at the boundary between a semiconductor structure, such as diffusion regions, and the deposited conductor. Localized heat may be generated at the target location through precise laser application, current generation through the target location, or a combination thereof.

Abstract translation: 在半导体衬底中研磨局部沟槽或接入孔以限定用于电路编辑的集成电路的结构的接入点。 导电体如聚焦离子束工具沉积在入口孔中，并且局部热被施加到用于硅化物形成的导体上，特别是在诸如扩散区域的半导体结构与沉积导体之间的边界处。 可以通过精确的激光施加，通过目标位置的电流产生或其组合在目标位置产生局部化的热量。

公开(公告)号：US20060076503A1

公开(公告)日：2006-04-13

申请号：US11222932

申请日：2005-09-08

Applicant: Chun-Cheng Tsao

Inventor： Chun-Cheng Tsao

IPC: H01J3/14 ,  G21K5/10 ,  G01K1/08 ,  A61N5/00

CPC classification number: H01J37/3056 ,  H01J37/228 ,  H01J2237/2482 ,  H01J2237/31749 ,  H01L21/76892 ,  H01L21/76898

Abstract: An optical coupling apparatus for a dual column charged particle beam tool allowing both optical imaging of an area of an integrated circuit, as well as localized heating of the integrated circuit to form silicide. In one embodiment, optical paths from a whitelight source and a laser source are coupled together by way of first and second beam splitters so that a single optical port of the dual column tool may be utilized for both imaging and heating. In another embodiment, a single laser source is employed to provide both illumination for standard microscopy-type imaging, as well as localized heating. In a third embodiment, a single laser source provides heating along with localized illumination for confocal scanning microscopy-type imaging.

公开(公告)号：US06955930B2

公开(公告)日：2005-10-18

申请号：US10161272

申请日：2002-05-30

Applicant: Erwan Le Roy ,  Chun-Cheng Tsao

Inventor： Erwan Le Roy ,  Chun-Cheng Tsao

IPC: H01J37/30 ,  H01J37/305 ,  H01L21/3065 ,  H01L21/66

CPC classification number: H01J37/3005 ,  H01J37/3056 ,  H01J2237/30466 ,  H01L21/3065

Abstract: Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The process includes a precise optical endpointing technique to monitor the remaining thickness of the semiconductor substrate at the floor of the trench. It is important to terminate etching of the trench so that the trench floor extends as close to the active semiconductor structures as desired and yet is not detrimental to device operation. This is done without introducing a need for any additional tool. This is carried out using an infra-red optical technique which observes the interference fringes generated by the reflections from the silicon substrate surface and from semiconductor device circuitry layers to quantify the remaining semiconductor substrate thickness in the trench.

Abstract translation: 用于从集成电路衬底的背面暴露诸如金属化层的选定部分的集成电路器件的选定特征的装置和方法，而不干扰诸如有源半导体区域的器件的相邻特征。 这是通过FIB（聚焦离子束）蚀刻工艺结合光学显微镜的观察来进行的，以通过衬底形成沟槽。 该方法包括精确的光学终点技术，以监测沟槽底部的半导体衬底的剩余厚度。 重要的是终止沟槽的蚀刻，使得沟槽底板根据需要延伸到接近有源半导体结构，并且不会对器件操作产生不利影响。 这不需要任何额外的工具就可以完成。 这使用红外光学技术进行，该技术观察由硅衬底表面和半导体器件电路层的反射产生的干涉条纹，以量化沟槽中剩余的半导体衬底厚度。