公开(公告)号：US11942468B2

公开(公告)日：2024-03-26

申请号：US17303251

申请日：2021-05-25

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Aleksey Khenkin ,  Justin Richardson ,  Michael Robinson ,  David Patten

IPC: H03F3/195 ,  H01L21/78 ,  H01L23/498 ,  H01L23/66 ,  H01L27/02 ,  H03F3/187 ,  H03F3/45

CPC classification number: H01L27/0207 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/66 ,  H03F3/187 ,  H03F3/45475 ,  H01L2223/6644 ,  H03F2200/03

Abstract: A packaged semiconductor die may include a package terminal array comprising a plurality of terminals, wherein a spacing between the plurality of terminals of the ball grid array is less than 0.5 mm. First and second high-voltage circuits of the die may output a differential signal to a first and second terminal that may exceed 15 volts, in which the first high-voltage circuit and the second high-voltage circuit are positioned symmetrically around an axis and in which the first terminal and the second terminal are located at an edge of the package terminal array. A low-voltage circuit may be coupled to a third terminal and positioned between the first high-voltage circuit and the second high-voltage circuit, wherein the low-voltage circuit comprises circuitry organized in columns aligned along an axis and having a width defined by a fraction of the terminal spacing pitch.

公开(公告)号：US20210287841A1

公开(公告)日：2021-09-16

申请号：US17173486

申请日：2021-02-11

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Aleksey S. Khenkin ,  David Patten ,  Jun Yan

IPC: H01F27/28 ,  H01F27/24 ,  H01F17/00

Abstract: A method for constructing a solenoid inductor includes positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and using a layered process to perform said positioning the inner and outer windings. The layered process includes processing a first conducting layer as a bottom layer of the outer winding, above processing a first dielectric layer, above processing a second conducting layer as a bottom layer of the inner winding, above processing a second dielectric layer, above processing a magnetic core layer, above processing a third dielectric layer, above processing a third conducting layer as a top layer of the inner winding, above processing a fourth dielectric layer, above processing a fourth conducting layer as a top layer of the outer winding, above processing a fifth dielectric layer, and the inner and outer windings are electrically connected.

公开(公告)号：US10735868B2

公开(公告)日：2020-08-04

申请号：US16179237

申请日：2018-11-02

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Rkia Achehboune ,  Dimitris Drogoudis ,  Roberto Brioschi ,  Aleksey Sergeyevich Khenkin ,  David Patten

IPC: H04R19/04 ,  B81B7/02 ,  H04R1/04 ,  H04R19/00

Abstract: A package for a MEMS device, the package comprising a MEMS transducer within a chamber of the package; and a package substrate, wherein an upper surface of the package substrate defines at least part of a surface of the chamber; wherein the package substrate comprises a plurality of metal layers, the package substrate further comprising at least a part of a filter circuit for filtering RF signals, wherein a first metal layer is provided in a first plane of the substrate and wherein a resistor of the filter circuit is provided in a plane below the first plane.