公开(公告)号：US20220384413A1

公开(公告)日：2022-12-01

申请号：US17303251

申请日：2021-05-25

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Aleksey Khenkin ,  Justin Richardson ,  Michael Robinson ,  David Patten

IPC: H01L27/02 ,  H01L23/66 ,  H01L21/78 ,  H01L23/498 ,  H03F3/187 ,  H03F3/45

Abstract: A packaged semiconductor die may include a package terminal array comprising a plurality of terminals, wherein a spacing between the plurality of terminals of the ball grid array is less than 0.5 mm. First and second high-voltage circuits of the die may output a differential signal to a first and second terminal that may exceed 15 volts, in which the first high-voltage circuit and the second high-voltage circuit are positioned symmetrically around an axis and in which the first terminal and the second terminal are located at an edge of the package terminal array. A low-voltage circuit may be coupled to a third terminal and positioned between the first high-voltage circuit and the second high-voltage circuit, wherein the low-voltage circuit comprises circuitry organized in columns aligned along an axis and having a width defined by a fraction of the terminal spacing pitch.

公开(公告)号：US11811370B2

公开(公告)日：2023-11-07

申请号：US17502689

申请日：2021-10-15

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Ramin Zanbaghi ,  Lingli Zhang ,  Wei Xu ,  Justin Richardson ,  John L. Melanson

IPC: H03F3/217 ,  G01R19/25

CPC classification number: H03F3/217 ,  G01R19/2506 ,  H03F2200/375

Abstract: A system for sensing an electrical quantity may include a sensing stage configured to sense the electrical quantity and generate a sense signal indicative of the electrical quantity, wherein the electrical quantity is indicative of an electrical signal generated by a Class-DG amplifier configured to drive a load wherein the Class-DG amplifier has multiple signal-level common modes and a common-mode compensator configured to compensate for changes to a common-mode voltage of a differential supply voltage of the driver occurring when switching between signal-level common modes of the Class-DG amplifier.

公开(公告)号：US11942468B2

公开(公告)日：2024-03-26

申请号：US17303251

申请日：2021-05-25

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Aleksey Khenkin ,  Justin Richardson ,  Michael Robinson ,  David Patten

IPC: H03F3/195 ,  H01L21/78 ,  H01L23/498 ,  H01L23/66 ,  H01L27/02 ,  H03F3/187 ,  H03F3/45

CPC classification number: H01L27/0207 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/66 ,  H03F3/187 ,  H03F3/45475 ,  H01L2223/6644 ,  H03F2200/03

Abstract: A packaged semiconductor die may include a package terminal array comprising a plurality of terminals, wherein a spacing between the plurality of terminals of the ball grid array is less than 0.5 mm. First and second high-voltage circuits of the die may output a differential signal to a first and second terminal that may exceed 15 volts, in which the first high-voltage circuit and the second high-voltage circuit are positioned symmetrically around an axis and in which the first terminal and the second terminal are located at an edge of the package terminal array. A low-voltage circuit may be coupled to a third terminal and positioned between the first high-voltage circuit and the second high-voltage circuit, wherein the low-voltage circuit comprises circuitry organized in columns aligned along an axis and having a width defined by a fraction of the terminal spacing pitch.