-
公开(公告)号：US12166457B2
公开(公告)日：2024-12-10
申请号：US18204356
申请日：2023-05-31
Inventor： John L. Melanson , Cory J. Peterson , Chandra Prakash , Ramin Zanbaghi , Eric Kimball
Abstract: Amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include multiple driver circuits and a control circuit. The control circuit selects between actively operating selected ones of the multiple driver circuits or all of the multiple driver circuits, according to an input signal to be reproduced by one or more of the multiple amplifier driver circuits. The control circuit determines a splice point at which the control circuit selects between actively operating selected ones of the multiple driver circuits or all of the multiple driver circuits.
-
公开(公告)号：US12113488B2
公开(公告)日：2024-10-08
申请号：US17940332
申请日：2022-09-08
Inventor： Chandra Prakash , Cory J. Peterson , Eric Kimball
CPC classification number: H03F1/3205 , H03F3/217 , H03F2200/03
Abstract: An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage. Each particular buffer of the plurality of buffers may include a buffering subcircuit configured to buffer the respective component of the differential pulse-width modulation input signal associated with the particular buffer in order to generate the respective buffered component and a biasing subcircuit configured to limit a magnitude of the respective component of the differential pulse-width modulation input signal driven to circuitry of the buffering subcircuit for driving the respective buffered component.
-
公开(公告)号：US11309853B1
公开(公告)日：2022-04-19
申请号：US17161815
申请日：2021-01-29
Inventor： Cory J. Peterson , Chandra Prakash , Ramin Zanbaghi , Eric Kimball
Abstract: A class-D amplifier includes a first differential modulator circuit, a first driver circuit including a first high-side switch and a first low-side switch. An input of the first driver circuit may be coupled to a first output of the first differential modulator circuit so that the first differential modulator circuit controls the first driver circuit. The class-D amplifier may also include a second driver circuit including a second high-side switch and a second low-side switch coupling the second and control logic that selects between a single-ended operating state and a differential operating state of the class-D amplifier circuit. The control logic may selectively determine the input of the second driver circuit in conformity with a current operating state of the class-D amplifier circuit so that the first differential modulator circuit controls the second driver circuit when the differential operating state is selected.
-
公开(公告)号：US11290071B2
公开(公告)日：2022-03-29
申请号：US17003564
申请日：2020-08-26
Inventor： Ramin Zanbaghi , Cory J. Peterson , Anand Ilango , Eric Kimball
IPC: H03F3/217 , H03F3/45 , H03F1/38 , G05F1/46 , H04R1/10 , G01R1/20 , G01R19/175 , G01R19/165
Abstract: A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a first sense resistor coupled between the first high-side switch and the supply voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the first sense resistor when the first high-side switch is activated. The current sensing circuitry may also include a second sense resistor coupled between the second high-side switch and the supply voltage, such that an output current through the load causes a second sense voltage proportional to the output current across the second sense resistor when the second high-side switch is activated. The system may also include measurement circuitry configured to measure the first sense voltage and the second sense voltage to determine the output current.
-
15.发明授权公开(公告)号：US11750157B2
公开(公告)日：2023-09-05
申请号：US17667234
申请日：2022-02-08
Inventor： Ramin Zanbaghi , Cory J. Peterson , Eric Kimball
CPC classification number: H03F3/2173 , G01R1/203 , G01R19/0092 , H03K4/06 , H03K7/08 , H03F2200/351 , H03F2200/462 , H03F2200/481
Abstract: A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a sense resistor, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the sense resistor. The system may additionally include a modulator for generating a differential pulse-width modulation driving signal to the first high-side switch, the second high-side switch, the first low-side switch, and the second low-side switch and pilot tone injection circuitry configured to inject a periodic pilot tone into the differential pulse-width modulation driving signal at a pilot tone frequency.
-
Patent Agency Ranking
公开(公告)号：US11500406B2
公开(公告)日：2022-11-15
申请号：US17212124
申请日：2021-03-25
Inventor： Ramin Zanbaghi , Eric Kimball
Abstract: Current monitoring techniques are included in an electronic system that provides power to a load from a power output stage that supplies power to a load. Multiple current control devices form the power output stage in series with multiple sense resistors that provide corresponding sense voltages indicative of current provided through the multiple current control devices to the load in the same or different time intervals. A calibration control circuit controls injection of current through the multiple sense resistors individually and measures the corresponding sense voltages generated by the current to determine resistance values of the multiple sense resistors. A correction subsystem computes a first ratio of a first resistance to a second resistance and a second ratio of a third resistance to a fourth resistance of the multiple sense resistors, and controls compensation for a difference between the first ratio and the second ratio to remove the measurement error.
-
公开(公告)号：US11489498B1
公开(公告)日：2022-11-01
申请号：US17338160
申请日：2021-06-03
Inventor： Chandra Prakash , Cory J. Peterson , Eric Kimball
Abstract: An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage. Each particular buffer of the plurality of buffers may include a buffering subcircuit configured to buffer the respective component of the differential pulse-width modulation input signal associated with the particular buffer in order to generate the respective buffered component and a biasing subcircuit configured to limit a magnitude of the respective component of the differential pulse-width modulation input signal driven to circuitry of the buffering subcircuit for driving the respective buffered component.
-
公开(公告)号：US11474216B2
公开(公告)日：2022-10-18
申请号：US16812920
申请日：2020-03-09
Inventor： Eric Kimball , Kyriaki Fotopoulou
IPC: G01J1/44 , G01S7/4863 , G01S17/10 , G01S7/497 , G01S7/489
Abstract: A method may include operating a single-photon avalanche diode (SPAD) in a first mode to determine a light intensity level associated with the SPAD, operating the SPAD in a second mode wherein a reverse bias voltage is applied in the second mode to bias the SPAD beyond its breakdown voltage, such that the SPAD operates in a detection mode, and determining a magnitude of the bias voltage applied to the SPAD in the second mode based on the light intensity level determined in the first mode.
-
公开(公告)号：US20220247367A1
公开(公告)日：2022-08-04
申请号：US17589047
申请日：2022-01-31
Inventor： John L. Melanson , Cory J. Peterson , Chandra Prakash , Ramin Zanbaghi , Eric Kimball
Abstract: Class-D amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include a first H-bridge driver circuit and a second H-bridge driver circuit. The class-D amplifier circuits also include a control circuit having an input for receiving an input signal to be reproduced by the class-D amplifier circuit. The control circuit has outputs coupled to inputs of the first and second H-bridge drivers, and includes one or more modulators. The control circuit selects between actively operating a selected one of the driver circuits or both, according to the signal to be reproduced, while setting an unselected driver circuit to turn either a high-side switch or a low-side switch of the unselected one of the first driver circuit or the second driver circuit fully on for at least some cycles of the one or more modulators.
-
公开(公告)号：US11329617B1
公开(公告)日：2022-05-10
申请号：US17151877
申请日：2021-01-19
Inventor： Cory J. Peterson , Chandra Prakash , Ramin Zanbaghi , Eric Kimball
Abstract: Class-D amplifiers and modulators therefor provide control of the DC operating point of the outputs of the amplifiers. The modulators generate a sum and difference signal using combiners and introduce the sum signal to a reference input of the quantizer, while the quantization input of the quantizer receives the difference signal. A difference mode loop filter circuit may filter the difference signal and a common mode loop filter may filter the sum signal. Outputs of the quantizer operate a pair of switching circuits to provide either a differential output with the sum signal set to a constant voltage and the difference signal provided by the signal to be reproduced, or a pair of single-ended outputs with the individual input signals used to generate the sum and difference signal, and selection of a differential or dual single-ended operating mode may be performed by a control circuit that reconfigures the combiners.
-
-
-
-
-
-
-
-
-
Search Results
22
records
(took 0.016 seconds)
