公开(公告)号：US20230083300A1

公开(公告)日：2023-03-16

申请号：US17957614

申请日：2022-09-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Nariankadu D. Hemkumar ,  Christopher Jackson ,  Younes Djadi ,  Nathan Daniel Pozniak Buchanan

IPC: G06F9/38 ,  G06F9/4401

Abstract: A distributed processing system with multiple systems connected by an inter-system communication interface. Each system has a memory programmed with multiple firmware images each having a distinct entry point, a processor, a writable (by another system of the distributed processing system) hardware register initially seeded with an initial firmware image entry point, and a controller external to the processor that, prior to an initial reset, reads the entry point from the hardware register and causes the processor to begin fetching instructions at the initial entry point. Prior to a subsequent reset of the processor, the external controller facilitates a transition to another firmware image by reading its entry point from the hardware register and causing the processor to begin fetching instructions at the other entry point. Each system may have multiple processors and multiple associated hardware registers writeable by another processor of the system or a by host processor.

公开(公告)号：US20210356843A1

公开(公告)日：2021-11-18

申请号：US17320528

申请日：2021-05-14

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Sachin Deo ,  Nariankadu D. Hemkumar ,  Akhilesh Persha ,  Younes Djadi

IPC: G03B13/36 ,  G03B5/04

Abstract: A system includes primary and secondary devices (e.g., camera controllers that drive voice coil motors) each having respective outputs and a communication link. The primary device includes first and second hardware timers, each of which expires at a time derived from a periodic control loop trigger. At first timer expiration, the primary transmits first updated values to the secondary. At second timer expiration, primary device hardware picks up and applies second updated values to the primary device outputs. In response to receiving the first updated values from the primary device, the secondary device applies the received first updated values to its outputs. The primary/secondary device combination provide a sufficient number of total outputs that they could not individually provide and further synchronize the outputs with small skew through the timers, which are programmable to also accommodate processing of inputs (e.g., from voice coil motor sensors) to compute the outputs.

公开(公告)号：US12164925B2

公开(公告)日：2024-12-10

申请号：US17957614

申请日：2022-09-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Nariankadu D. Hemkumar ,  Christopher Jackson ,  Younes Djadi ,  Nathan Daniel Pozniak Buchanan

IPC: G06F9/38 ,  G06F9/4401

Abstract: A distributed processing system with multiple systems connected by an inter-system communication interface. Each system has a memory programmed with multiple firmware images each having a distinct entry point, a processor, a writable (by another system of the distributed processing system) hardware register initially seeded with an initial firmware image entry point, and a controller external to the processor that, prior to an initial reset, reads the entry point from the hardware register and causes the processor to begin fetching instructions at the initial entry point. Prior to a subsequent reset of the processor, the external controller facilitates a transition to another firmware image by reading its entry point from the hardware register and causing the processor to begin fetching instructions at the other entry point. Each system may have multiple processors and multiple associated hardware registers writeable by another processor of the system or a by host processor.

公开(公告)号：US20240201729A1

公开(公告)日：2024-06-20

申请号：US18067307

申请日：2022-12-16

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Trenton Henry ,  Nariankadu D. Hemkumar

IPC: G06F1/12 ,  G06F1/14

CPC classification number: G06F1/12 ,  G06F1/14

Abstract: This disclosure relates to instrumenting of integrated circuits, and particularly with providing synchronized time stamps for logging data from multiple components. An example method includes injecting code in a read only memory (ROM) that performs the logging with time stamps. The method may include receiving, from a first component, data describing a first event with a first time stamp synchronized to a global clock; receiving, from a second component, data describing a second event with a second time stamp synchronized to the global clock; and generating a report comprising the first event and the second event, wherein the first event is synchronized with the second event. Other aspects are also disclosed.

公开(公告)号：US11846973B1

公开(公告)日：2023-12-19

申请号：US17982916

申请日：2022-11-08

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Sachin Deo ,  Younes Djadi ,  Nariankadu D. Hemkumar ,  Junsong Li ,  Wai-Shun Shum ,  Franz Weller

IPC: G06F13/10 ,  G06F13/24

CPC classification number: G06F13/24 ,  G06F13/102

Abstract: A multicore processor may include a plurality of cores including at least a first core and a second core, a shared peripheral comprising a plurality of interrupt register banks including at least a first interrupt register bank dedicated to the first core and a second interrupt register bank dedicated to the second core, and a plurality of communications bridges, including at least a first bridge interfaced between the first core and the shared peripheral and at least a second bridge interfaced between the second core and the shared peripheral. The first core may be configured to program the first interrupt register bank via the first bridge to configure the shared peripheral for access by the first core. The second core may be configured to program the second interrupt register bank via the second bridge to configure the shared peripheral for access by the second core.

公开(公告)号：US20230080059A1

公开(公告)日：2023-03-16

申请号：US17957708

申请日：2022-09-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Nariankadu D. Hemkumar ,  Christopher Jackson ,  Younes Djadi ,  Nathan Daniel Pozniak Buchanan

IPC: G06F9/4401 ,  G06F9/38 ,  G06F8/65

Abstract: A system has a memory programmed with multiple firmware images each having an associated distinct entry point, a processor, a writable hardware register, and a controller external to the processor that, prior to each reset of a sequence of resets of the processor, reads the entry point of a firmware image from the hardware register and causes the processor to begin fetching instructions at the entry point read from the hardware register. The firmware images include boot, mission mode, and at least one other firmware image. The memory may be writeable with a modifiable version of a post-production mission mode, debug, prototype, or patched ROM firmware image. A second controller writes a second entry point to the hardware register prior to an initial reset such that the external controller reads the second entry point and causes fetching instructions at the second entry point rather than the initial entry point.

公开(公告)号：US10963187B2

公开(公告)日：2021-03-30

申请号：US16437746

申请日：2019-06-11

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Nathan Buchanan ,  Roshan Kamath ,  Nariankadu D. Hemkumar ,  Younes Djadi ,  Sachin Deo ,  Eric B. Smith

IPC: G06F3/06 ,  H04N5/232

Abstract: A system for reading a plurality of subset views of an evolving data store may include for each subset view, a plurality of memory buffers comprising at least three buffers. The system may also include control circuitry for controlling the plurality of memory buffers of the plurality of subset views, the control circuitry configured to maintain, for each subset view, a variable defining a most-recently updated buffer of the plurality of buffers such that a read request for such subset view will respond with data of the most-recently updated buffer of such subset view; and responsive to an update of data of the evolving data store: (i) determine, for each subset view, a selected data buffer of the plurality of buffers other than the most-recently updated buffer for such subset view to write updated subset view information; (ii) cause, for each subset view, the updated subset view information for such subset view to be written to the selected data buffer for such subset view; and (iii) substantially simultaneously across all of the plurality of subset views, update the variables defining the most-recently updated buffer of the plurality of subset views such that a subsequent read request for a subset view will respond with the updated subset view information for such subset view.