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公开(公告)号：US11844157B2
公开(公告)日：2023-12-12
申请号：US17860918
申请日：2022-07-08
Inventor： Dave Smith , Saurabh Singh , Andrew Buist , Paulius Cerebiejus , Mark J. McCloy-Stevens , Terence A. Orr
IPC: H05B45/345 , H03F3/04
CPC classification number: H05B45/345 , H03F3/04 , H03F2200/129
Abstract: The present disclosure relates to current control circuitry for controlling a current through a load, the current control circuitry comprising: amplifier circuitry; reference voltage generator circuitry configured to supply a fixed reference voltage to a first input of the amplifier circuitry; an output stage comprising: a control terminal coupled to an output of the amplifier circuitry; a current input terminal configured to be coupled to the load; a current output terminal; a clock-controlled variable resistance coupled to the current output terminal of the output stage, wherein a resistance of the variable resistance is based on a digital code input to the variable resistance; and a feedback path between the current output terminal of the output stage and a second terminal of the amplifier circuitry for providing a feedback voltage to a second input of the amplifier circuitry.
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公开(公告)号：US11799428B2
公开(公告)日：2023-10-24
申请号：US17573000
申请日：2022-01-11
Inventor： Saurabh Singh , Chandra B. Prakash
CPC classification number: H03F3/04 , G01D18/00 , H03F2200/375
Abstract: A method may include receiving, by a calibration circuit, an output of a subsystem comprising the sensor and the analog front end. The method may further include separating the output individually into the sensor offset and the amplifier offset by using inherent properties of separate frequency ranges for the sensor offset and the amplifier offset. The method may also include calibrating, by the calibration circuit, the sensor offset by determining a first calibration value for the sensor offset such that the output approximates zero during an idle-channel condition. The method may additionally include calibrating, by the calibration circuit, the amplifier offset by determining a second calibration value for the amplifier offset such that the output approximates zero during the idle-channel condition.
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Patent Agency Ranking
公开(公告)号：US11316523B1
公开(公告)日：2022-04-26
申请号：US17308741
申请日：2021-05-05
Inventor： Saurabh Singh , Jaimin Mehta , Sriram Balasubramanian , Anindya Bhattacharya
Abstract: A system may include a digitally-controlled oscillator configured to generate an output clock signal based on a control signal received at an input of the digitally-controlled oscillator and a control circuit configured to calculate an error signal between the output clock signal and an external reference clock signal, filter the error signal to generate a correction signal, generate the control signal based on the correction signal, and switch between a first mode of operation and a second mode of operation without artifacts on the correction signal during switching between the first mode and the second mode.
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公开(公告)号：US11070177B2
公开(公告)日：2021-07-20
申请号：US16562856
申请日：2019-09-06
Inventor： Saurabh Singh , Vamsikrishna Parupalli , Stewart Kenly , Eric B. Smith
Abstract: A system may include an output stage comprising a single-ended driver for driving a load at an output of the output stage, a loop filter coupled at its input to the output of the output stage and configured to minimize an error between a target current signal received by the loop filter and an output current driven on the load, and control circuitry configured to, when the load current is driven in a manner such that the load current changes polarity, reset a state variable of the loop filter.
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公开(公告)号：US09780800B1
公开(公告)日：2017-10-03
申请号：US15269043
申请日：2016-09-19
Inventor： Aniruddha Satoskar , Daniel J. Allen , Edmund Mark Schneider , Saurabh Singh , John L. Melanson
IPC: H03M1/06
CPC classification number: H03M1/0626 , H03M1/0607 , H03M1/0612 , H03M1/188
Abstract: A method may include processing an analog input signal with a first processing path configured to generate a first digital signal based on the analog input signal; processing the analog input signal with a second processing path configured to generate a second digital signal based on the analog input signal, and adapting a response of an adaptive filter configured to generate a filtered digital signal from the second digital signal to reduce a difference between the filtered digital signal and the first digital signal. The method may additionally or alternatively include determining nonlinearities present in the second processing path based on comparison of the first digital signal and the second digital signal, and applying a linear correction to the second digital signal to generate a corrected second digital signal with decreased nonlinearity from that of the second digital signal.
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公开(公告)号：US11223368B1
公开(公告)日：2022-01-11
申请号：US17061939
申请日：2020-10-02
Inventor： Chandra Prakash , Saurabh Singh
IPC: H03M3/00
Abstract: A switched-capacitor delta-sigma data converter circuit includes compensation for voltage reference error that may cause non-linearity and inter-channel crosstalk. The circuit includes a voltage reference circuit, an integrator, a quantizer that quantizes the output of the integrator and a reference feedback switched-capacitor network that provides feedback charge quanta to the integrator that represents an output of the quantizer, so that the output of the quantizer, on average, represents an input signal provided to the integrator. In addition, a compensation switched-capacitor network is included for drawing dummy load charge quanta from the voltage reference output that is not provided to the integrator so that a total charge drawn from the voltage reference output when the reference feedback switched-capacitor network is coupled to the voltage reference output does not vary as the input voltage varies.
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公开(公告)号：US09762255B1
公开(公告)日：2017-09-12
申请号：US15269087
申请日：2016-09-19
Inventor： Aniruddha Satoskar , Daniel J. Allen , Edmund Mark Schneider , Saurabh Singh
CPC classification number: H03M1/0626 , H03M1/0607 , H03M1/0612 , H03M1/183 , H03M1/188
Abstract: A method may include processing an analog input signal to generate a first digital signal in accordance with a first analog gain, processing the analog input signal to generate a second digital signal in accordance with a second analog gain, and generating a digital output signal of the processing system from one or both of the first digital signal and the second digital signal based on a magnitude of the analog input signal and setting the first analog gain based on the magnitude of the analog input when the digital output signal is generated from the second digital signal.
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