公开(公告)号：US20200133455A1

公开(公告)日：2020-04-30

申请号：US16422543

申请日：2019-05-24

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Hamid SEPEHR ,  Pablo PESO PARADA ,  Willem ZWART ,  Tom BIRCHALL ,  Michael Allen KOST ,  Tejasvi DAS ,  Siddharth MARU ,  Matthew BEARDSWORTH ,  Bruce E. DUEWER

IPC: G06F3/0488 ,  G06F3/041

Abstract: A force sensing system for determining if a user input has occurred, the system comprising: an input channel, to receive an input from at least one force sensor; an activity detection stage, to monitor an activity level of the input from the at least one force sensor and, responsive to an activity level which may be indicative of a user input being reached, to generate an indication that an activity has occurred at the force sensor; and an event detection stage to receive said indication, and to determine if a user input has occurred based on the received input from the at least one force sensor.

公开(公告)号：US20180176034A1

公开(公告)日：2018-06-21

申请号：US15898839

申请日：2018-02-19

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem ZWART ,  John Bruce BOWLERWELL ,  Michael PAGE ,  Alastair BOOMER

IPC: H04L12/40 ,  H04L5/14 ,  G06F13/42 ,  G06F13/40

CPC classification number: H04L12/40013 ,  G06F13/4027 ,  G06F13/4282 ,  G06F13/4291 ,  G06F2213/0016 ,  H04L5/1476

Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.

公开(公告)号：US20160267028A1

公开(公告)日：2016-09-15

申请号：US15063902

申请日：2016-03-08

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem ZWART

IPC: G06F13/22 ,  G06F13/16 ,  G06F11/10 ,  H03M13/09

CPC classification number: G06F13/22 ,  G06F11/1004 ,  G06F13/1642 ,  G06F13/4282 ,  H03M13/09 ,  H04L12/403

Abstract: A method is provided for use in a host module, for identifying at least one accessory module on a bus, wherein the bus is configured to allow multiple accessory modules to be connected to the host module. The method includes sending a query to any accessory module connected to the bus, the query concerning whether the or each accessory module meets a specified criterion; and receiving synchronised responses from any accessory module that meets the specified criterion connected to the bus where said responses are specific to the query but non-specific to an effectively uniquely distinguishing feature of the individual module. It is then possible to determine from redundant information contained in an aggregate of the synchronised responses whether there is (a) no accessory module meeting the specified criterion, or (b) at least one accessory module meeting the specified criterion.

Abstract translation: 提供一种用于主机模块中的用于识别总线上的至少一个附件模块的方法，其中所述总线被配置为允许多个附件模块连接到所述主机模块。 该方法包括向连接到总线的任何附件模块发送查询，关于该附件模块或每个附件模块是否满足指定标准的查询; 以及接收来自任何附件模块的同步响应，所述附件模块满足连接到所述响应特定于所述查询的所述总线的指定标准，但是对于所述单独模块的有效唯一区分特征是非特定的。 然后可以从包含在同步响应的聚合中的冗余信息确定是否存在（a）不符合指定标准的附件模块，或（b）符合指定标准的至少一个附件模块。