公开(公告)号：US07372728B2

公开(公告)日：2008-05-13

申请号：US11738987

申请日：2007-04-23

Applicant: Cyrille Dray ,  Christophe Frey ,  Jean Lasseuguette ,  Sébastien Barasinski ,  Richard Fournel

Inventor： Cyrille Dray ,  Christophe Frey ,  Jean Lasseuguette ,  Sébastien Barasinski ,  Richard Fournel

IPC: G11C11/14

CPC classification number: G11C11/15

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.

Abstract translation: 随机存取存储器阵列包括排列成行和列的随机存取存储器元件。 每行的元素具有字线和写数字线，并且每列的元素具有位线和写位线。 用于每行的第一选择电路/晶体管具有耦合在写入数字线中的第一源极 - 漏极通路和耦合到字线的栅极端子。 用于每列的第二选择电路/晶体管具有在写位线中耦合的第二源 - 漏路径和耦合到位线的栅极端。 第一写入信号被施加到一个字线以激活对应于该一条字线的行的第一选择电路/晶体管，并且使得写入电流流过被激活的第一选择电路/晶体管的第一源极 - 漏极路径，并且 相应的写数字行将数据写入该行中的某些存储器元素。 第二写入信号被施加到一个位线以启动与该一个位线相对应的列的第二选择电路/晶体管，并且使得写入电流流过被致动的第二选择电路/晶体管的第二源极 - 漏极通路，并且 相应的写位线将数据写入该列中的至少一个存储器元件。

公开(公告)号：US07110315B2

公开(公告)日：2006-09-19

申请号：US10929359

申请日：2004-08-27

Applicant: Cyrille Dray

Inventor： Cyrille Dray

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C16/12

Abstract: A switch arrangement for switching a node between three supply voltages based on two control signals. The switch arrangement includes three circuits for connecting an output node with one of three nodes, each of which is set to a different voltage. The switch arrangement is controlled by six control signals that establish mutually exclusive switching modes and avoid combinational currents. The switch arrangement is also designed to allow the use of MOS transistors having a low nominal voltage, with a value that is lower than the highest voltage to be switched. The switch arrangement is particularly adapted to supply power to non-volatile memory cells.

Abstract translation: 一种用于基于两个控制信号在三个电源电压之间切换节点的开关装置。 开关装置包括用于将输出节点与三个节点之一连接的三个电路，每个节点被设置为不同的电压。 开关布置由六个控制信号控制，这些控制信号建立互斥开关模式并避免组合电流。 开关装置还被设计为允许使用具有低额定电压的MOS晶体管，其值低于要切换的最高电压。 开关装置特别适于向非易失性存储单元供电。

公开(公告)号：US20050219912A1

公开(公告)日：2005-10-06

申请号：US10511712

申请日：2003-01-31

Applicant: Philippe Gendrier ,  Cyrille Dray ,  Richard Fournel ,  Sebastien Poirier ,  Daniel Caspar ,  Philippe Candelier

Inventor： Philippe Gendrier ,  Cyrille Dray ,  Richard Fournel ,  Sebastien Poirier ,  Daniel Caspar ,  Philippe Candelier

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7881

Abstract: The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Abstract translation: 半导体存储器件包括具有单层栅极材料并且包括浮栅晶体管和控制栅的电可擦除可编程非易失性存储单元。 浮栅晶体管的源极，漏极和沟道区域形成控制栅极。 此外，存储单元包括位于栅极材料层的第一部分和与结合有控制栅极的第二有源区电隔离的第一半导体有源区之间的介电区。 该介电区随后形成隧道区，用于在电池擦除期间将存储在浮动栅极中的电荷转移到第一活性区。

公开(公告)号：US06728135B2

公开(公告)日：2004-04-27

申请号：US10228164

申请日：2002-08-26

Applicant: Cyrille Dray ,  Daniel Caspar ,  Richard Fournel

Inventor： Cyrille Dray ,  Daniel Caspar ,  Richard Fournel

IPC: G11C1600

CPC classification number: H01L29/42324 ,  H01L29/7887

Abstract: The FAMOS memory location comprises a single floating gate (GR) overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles (PF1, PF2) so as to define at least two electrodes in the active region. Memory location programming means (MC, SW) are capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.

Abstract translation: FAMOS存储器位置包括根据至少两个不对称重叠轮廓（PF1，PF2）与半导体衬底的有源表面重叠的单个浮动栅极（GR），以便在有源区域中限定至少两个电极。 存储器位置编程装置（MC，SW）能够选择性地向电极施加不同的预定偏置电压组，以便在存储器位置上赋予至少三个编程逻辑电平。

公开(公告)号：US09263121B2

公开(公告)日：2016-02-16

申请号：US13976403

申请日：2013-05-16

Applicant: Eric A. Karl ,  Yong-Gee Ng ,  Cyrille Dray

Inventor： Eric A. Karl ,  Yong-Gee Ng ,  Cyrille Dray

IPC: G11C5/14 ,  G11C11/419 ,  G11C11/417 ,  G11C11/414 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C5/147 ,  G11C11/413 ,  G11C11/414 ,  G11C11/417

Abstract: Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node.

Abstract translation: 描述了一种在写入辅助操作期间消耗低功率的存储器写入辅助装置。 该装置包括：电源节点; 可操作以调节所述电源节点上的电压的装置; 以及耦合到所述电源节点的反馈单元，所述反馈单元响应于所述电源节点上的电压的电压电平来控制所述装置。

公开(公告)号：US08335121B2

公开(公告)日：2012-12-18

申请号：US12829675

申请日：2010-07-02

Applicant: Cyrille Dray ,  Francois Jacquet ,  Sébastien Barasinski

Inventor： Cyrille Dray ,  Francois Jacquet ,  Sébastien Barasinski

IPC: G11C7/02

CPC classification number: G11C11/413

Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract translation: 提供了一种用于SRAM存储器信息存储的设备和相应的实现方法。 该设备由电源电压供电并且包括组合在基列中的基本单元的阵列，以及至少一个反射镜单元的至少一个反射镜列，其容易模拟基极柱中的单元的行为。 该装置还包括在立柱中的最大限制单元的反射镜列中的仿真装置，用于改变反射镜列的反射镜电源电压的装置和用于复制仿真基色列中的反射镜电源电压的装置。

公开(公告)号：US07795917B2

公开(公告)日：2010-09-14

申请号：US12009144

申请日：2008-01-15

Applicant: Sebastien Barasinski ,  Cyrille Dray

Inventor： Sebastien Barasinski ,  Cyrille Dray

IPC: H03K19/0175 ,  H03B1/00

CPC classification number: H03K19/01707

Abstract: A buffer circuit includes at least one part that is powered by a supply voltage by means of a first initialization transistor, and connected to the ground by means of a second initialization transistor. The circuit is capable of transferring, between an input and an output, an input signal including at least one rising edge and/or one falling edge. The circuit includes a first CMOS inverter, of which the input is connected to the input of the circuit, and of which the output is mounted in series with the input of a second CMOS inverter, with the output of the second CMOS inverter being connected to the output of the circuit. A circuit creates an overvoltage on one of the two inverters during operation.

Abstract translation: 缓冲电路包括借助于第一初始化晶体管由电源供电的至少一个部分，并通过第二初始化晶体管连接到地。 该电路能够在输入和输出之间传输包括至少一个上升沿和/或一个下降沿的输入信号。 该电路包括第一CMOS反相器，其中输入端连接到电路的输入端，其输出端与第二CMOS反相器的输入串联安装，第二CMOS反相器的输出端连接到 电路的输出。 电路在运行期间在两台逆变器之一上产生过电压。

公开(公告)号：US20090027987A1

公开(公告)日：2009-01-29

申请号：US11782418

申请日：2007-07-24

Applicant: Cyrille Dray ,  Stephany Bouniol ,  Magali Hage Hassan ,  Luc Palau

Inventor： Cyrille Dray ,  Stephany Bouniol ,  Magali Hage Hassan ,  Luc Palau

IPC: G11C7/00

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C29/24 ,  G11C29/50012

Abstract: An apparatus including a memory cell, a reference cell, a control unit, coupled to the memory cell and the reference cell, and configured to initiate write processes of the memory cell and the reference cell, and a detection unit, coupled to the reference cell, and configured to detect a write completion of the reference cell. Related methods are also disclosed.

Abstract translation: 一种装置，包括耦合到存储单元和参考单元的存储单元，参考单元，控制单元，并且被配置为启动存储单元和参考单元的写入处理;以及检测单元，耦合到参考单元 并且被配置为检测参考单元的写入完成。 还公开了相关方法。

公开(公告)号：US20080218211A1

公开(公告)日：2008-09-11

申请号：US12009144

申请日：2008-01-15

Applicant: Sebastien Barasinski ,  Cyrille Dray

Inventor： Sebastien Barasinski ,  Cyrille Dray

IPC: H03K19/0175

CPC classification number: H03K19/01707

Abstract: A buffer circuit includes at least one part that is powered by a supply voltage by means of a first initialization transistor, and connected to the ground by means of a second initialization transistor. The circuit is capable of transferring, between an input and an output, an input signal including at least one rising edge and/or one falling edge. The circuit includes a first CMOS inverter, of which the input is connected to the input of the circuit, and of which the output is mounted in series with the input of a second CMOS inverter, with the output of the second CMOS inverter being connected to the output of the circuit. A circuit creates an overvoltage on one of the two inverters during operation.

Abstract translation: 缓冲电路包括借助于第一初始化晶体管由电源供电的至少一个部分，并通过第二初始化晶体管连接到地。 该电路能够在输入和输出之间传输包括至少一个上升沿和/或一个下降沿的输入信号。 该电路包括第一CMOS反相器，其中输入端连接到电路的输入端，其输出端与第二CMOS反相器的输入串联安装，第二CMOS反相器的输出端连接到 电路的输出。 电路在运行期间在两台逆变器之一上产生过电压。

公开(公告)号：US07333362B2

公开(公告)日：2008-02-19

申请号：US10511712

申请日：2003-01-31

Applicant: Philippe Gendrier ,  Cyrille Dray ,  Richard Fournel ,  Sébastien Poirier ,  Daniel Caspar ,  Philippe Candelier

Inventor： Philippe Gendrier ,  Cyrille Dray ,  Richard Fournel ,  Sébastien Poirier ,  Daniel Caspar ,  Philippe Candelier

IPC: G11C16/04

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7881

Abstract: The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Abstract translation: 半导体存储器件包括具有单层栅极材料并且包括浮栅晶体管和控制栅的电可擦除可编程非易失性存储单元。 浮栅晶体管的源极，漏极和沟道区域形成控制栅极。 此外，存储单元包括位于栅极材料层的第一部分和与结合有控制栅极的第二有源区电隔离的第一半导体有源区之间的介电区。 该介电区随后形成隧道区，用于在电池擦除期间将存储在浮动栅极中的电荷转移到第一活性区。