公开(公告)号：US20230143506A1

公开(公告)日：2023-05-11

申请号：US17399375

申请日：2021-08-11

Applicant: D-WAVE SYSTEMS INC.

Inventor： Mark W. Johnson ,  Paul I. Bunyk ,  Andrew J. Berkley ,  Richard G. Harris ,  Kelly T. R. Boothby ,  Loren J. Swenson ,  Emile M. Hoskinson ,  Christopher B. Rich ,  Jan E. S. Johansson

IPC: H10N60/12 ,  G06N10/00 ,  H10N60/80

CPC classification number: H10N60/124 ,  G06N10/00 ,  H10N60/805

Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

公开(公告)号：US20200379768A1

公开(公告)日：2020-12-03

申请号：US16854396

申请日：2020-04-21

Applicant: D-WAVE SYSTEMS INC.

Inventor： Andrew J. Berkley ,  Ilya V. Perminov ,  Mark W. Johnson ,  Christopher B. Rich ,  Fabio Altomare ,  Trevor M. Lanting

IPC: G06F9/38 ,  G06F16/901 ,  G06N10/00

Abstract: A hybrid processor includes a classical (digital) processor and a quantum processor and implements a calibration procedure to calibrate devices in the quantum processor. Parameter measurements are defined as vertices in a directed acyclic graph. Dependencies between measurements are defined as directed edges between vertices. The calibration procedure orders the vertices, respecting the order of the dependencies while at least attempting to reduce the time needed to perform all the measurements. The calibration procedure provides a level of abstraction to allow non-expert users to use the calibration procedure. Each vertex has a set of attributes defining the status of the measurement, time of the measurement and value of the measurement.

公开(公告)号：US09355365B2

公开(公告)日：2016-05-31

申请号：US14255561

申请日：2014-04-17

Applicant: D-WAVE SYSTEMS INC.

Inventor： Andrew J. Berkley ,  Mark W. Johnson ,  Paul I. Bunyk

IPC: H01L39/00 ,  G06N99/00 ,  B82Y10/00 ,  H01L23/532 ,  H01L27/18

CPC classification number: G06N99/002 ,  B82Y10/00 ,  H01L23/53285 ,  H01L27/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element. At least one of the first inductive coupling element and the second inductive coupling element may be coupled to a superconducting programmable device, such as a superconducting qubit.

Abstract translation: 超导集成电路可以包括具有内部感应耦合元件和外部感应耦合元件的磁通量变换器，该外部感应耦合元件沿其长度的至少一部分围绕内部感应耦合元件。 磁通变压器可以具有类似同轴的几何形状，使得第一感应耦合元件和第二感应耦合元件之间的互感与将第一内部感应耦合元件与第一外部电感耦合器分开的距离成亚线性比例 元件。 第一电感耦合元件和第二电感耦合元件中的至少一个可以耦合到超导可编程器件，例如超导量子位。

公开(公告)号：US20150363708A1

公开(公告)日：2015-12-17

申请号：US14734924

申请日：2015-06-09

Applicant: D-Wave Systems Inc.

Inventor： Mohammad H.S. Amin ,  Mark W. Johnson

IPC: G06N99/00 ,  G06F15/78

Abstract: A second problem Hamiltonian may replace a first problem Hamiltonian during evolution of an analog processor (e.g., quantum processor) during a first iteration in solving a first problem. This may be repeated during a second, or further successive iterations on the first problem, following re-initialization of the analog processor. An analog processor may evolve under a first non-monotonic evolution schedule during a first iteration, and second non-monotonic evolution schedule under second, or additional non-monotonic evolution schedule under even further iterations. A first graph and second graph may each be processed to extract final states versus a plurality of evolution schedules, and a determination made as to whether the first graph is isomorphic with respect to the second graph. An analog processor may evolve by decreasing a temperature of, and a set of quantum fluctuations, within the analog processor until the analog processor reaches a state preferred by a problem Hamiltonian.

Abstract translation: 在解决第一个问题的第一次迭代期间，第二个问题哈密尔顿算子可以在模拟处理器（例如，量子处理器）的演变期间替换第一个问题哈密尔顿算子。 在对模拟处理器进行重新初始化之后，可以在关于第一问题的第二次或进一步的连续迭代中重复这一点。 在第一次迭代期间，模拟处理器可以在第一非单调进化计划下演化，并且在甚至进一步迭代的第二非单调进化计划下进行第二非单调进化计划。 可以分别处理第一图和第二图以提取最终状态与多个进化计划，并且确定关于第一图表是否与第二图形是同构的。 模拟处理器可以通过降低模拟处理器内的温度和一组量子波动来演化，直到模拟处理器达到由问题哈密尔顿算子所优选的状态。