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11.发明授权High performance recoverable communication method and apparatus for write-only networks 失效用于只写网络的高性能可恢复通信方法和装置
公开(公告)号：US6049889A
公开(公告)日：2000-04-11
申请号：US6115
申请日：1998-01-13
摘要： A multi-node computer network includes a plurality of nodes coupled together via a data link. Each of the nodes includes a local memory, which further comprises a shared memory. Certain items of data that are to be shared by the nodes are stored in the shared portion of memory. Associated with each of the shared data items is a data structure. When a node sharing data with other nodes in the system seeks to modify the data, it transmits the modifications over the data link to the other nodes in the network. Each update is received in order by each node in the cluster. As part of the last transmission by the modifying node, an acknowledgement request is sent to the receiving nodes in the cluster. Each node that receives the acknowledgment request returns an acknowledgement to the sending node. The returned acknowledgement is written to the data structure associated with the shared data item. If there is an error during the transmission of the message, the receiving node does not transmit an acknowledgement, and the sending node is thereby notified that an error has occurred.
摘要翻译： 多节点计算机网络包括通过数据链路耦合在一起的多个节点。 每个节点包括本地存储器，其还包括共享存储器。 要由节点共享的某些数据项存储在存储器的共享部分中。 与每个共享数据项相关联的是数据结构。 当与系统中的其他节点共享数据的节点寻求修改数据时，它将数据链路上的修改发送到网络中的其他节点。 群集中的每个节点按顺序接收每个更新。 作为修改节点的最后一次传输的一部分，向群集中的接收节点发送确认请求。 接收确认请求的每个节点向发送节点返回确认。 返回的确认被写入与共享数据项相关联的数据结构。 如果在消息的发送期间存在错误，则接收节点不发送确认，并且由此通知发送节点发生了错误。
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12.发明授权Method and apparatus for managing multiple lock indicators in a multiprocessor computer system 失效用于在多处理器计算机系统中管理多个锁定指示器的方法和装置
公开(公告)号：US4858116A
公开(公告)日：1989-08-15
申请号：US44954
申请日：1987-05-01
CPC分类号： G06F9/52 , G06F13/4217 , G06F9/3004 , G06F9/30087
摘要： A computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to a memory or I/O node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processes in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the memory which indicates that the specified location is locked.
摘要翻译： 具有通过挂起总线互连的多个处理器的计算机系统提供采用多个锁定位的独占读取 - 修改 - 写入操作。 处理器产生互锁读命令，该命令作为通过挂起总线的传送被传送到存储器或I / O节点。 在处理器传输的每个总线周期之后，确认确认由存储器发送回处理器两个总线周期。 处理器传输（包括互锁读取命令）存储在存储器中的输入队列中，并依次由存储器进行处理。 对指定的存储器位置的第一联锁读取命令导致为该位置设置锁定位，以及包括要由存储器生成并存储在输出队列中的指定位置的内容的第一类型的响应消息。 存储器通过仲裁处理获得对待处理总线的访问，并且在启动互锁读取命令之后的未指定时间发送包括在联锁读取命令中指定的存储器位置的内容的响应消息。 从处理器到相同存储器位置的随后的互锁读取命令将导致拒绝对指定位置的访问以及存储器生成指示指定位置被锁定的第二类型的响应消息。
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13.发明授权Commander node method and apparatus for assuring adequate access to system resources in a multiprocessor 失效用于确保对多处理器中的系统资源的充分访问的指令器节点方法和装置
公开(公告)号：US5341510A
公开(公告)日：1994-08-23
申请号：US141466
申请日：1993-10-22
CPC分类号： G06F9/52
摘要： A multiple node computer system includes processor nodes, memory nodes, and input/output nodes interconnected on a pended bus. The system includes a lockout indicator which is set upon receipt of a locked response message by a processor node from a memory node in response to an interlock read command. The processors include a lockout check circuit responsive to the condition of the lockout indicator and will restrict generation of additional interlock read commands according to a predetermined access gating criterion until the lockout indicator is reset. In this manner, processor nodes of the system are assured equitable access to a memory node.
摘要翻译： 多节点计算机系统包括在挂起总线上互连的处理器节点，存储器节点和输入/输出节点。 该系统包括锁定指示器，该锁定指示器响应于互锁读取命令而从处理器节点从存储器节点接收到锁定的响应消息时被设置。 处理器包括响应于锁定指示器的状况的锁定检查电路，并且将根据预定的访问选通标准限制产生额外的互锁读取命令，直到锁定指示器被复位。 以这种方式，系统的处理器节点被确保公平地访问存储器节点。
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14.发明授权System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system 失效在多处理器计算机系统中实现同步挂起总线上的多个锁定指示器的系统
公开(公告)号：US4949239A
公开(公告)日：1990-08-14
申请号：US44466
申请日：1987-05-01
CPC分类号： G06F9/52 , G06F13/4217
摘要： A memory node in a computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to the memory node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processed in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the memory which indicates that the specified location is locked.
摘要翻译： 具有通过挂起总线互连的多个处理器的计算机系统中的存储器节点提供采用多个锁定位的排他读取 - 修改 - 写入操作。 处理器产生互锁读取命令，该命令作为通过挂起总线的传送被传送到存储器节点。 在处理器传输的每个总线周期之后，确认确认由存储器发送回处理器两个总线周期。 包括联锁读取命令的处理器传送存储在存储器中的输入队列中，然后由存储器进行处理。 对指定的存储器位置的第一联锁读取命令导致为该位置设置锁定位，以及包括要由存储器生成并存储在输出队列中的指定位置的内容的第一类型的响应消息。 存储器通过仲裁处理获得对待处理总线的访问，并且在启动互锁读取命令之后的未指定时间发送包括在联锁读取命令中指定的存储器位置的内容的响应消息。 从处理器到相同存储器位置的随后的互锁读取命令将导致拒绝对指定位置的访问以及存储器生成指示指定位置被锁定的第二类型的响应消息。
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15.发明授权Method and apparatus for assuring adequate access to system resources by processors in a multiprocessor computer system 失效用于通过多处理器计算机系统中的处理器确保对系统资源的充分访问的方法和装置
公开(公告)号：US4937733A
公开(公告)日：1990-06-26
申请号：US44952
申请日：1987-05-01
IPC分类号： G06F15/16 , G06F9/46 , G06F9/52 , G06F12/00 , G06F15/177
CPC分类号： G06F9/52
摘要： A multiple node computer system includes processor nodes, memory nodes, and input/output nodes interconnected on a pended bus. The system includes a lockout indicator which is set upon receipt of a locked response message by a processor node from a memory node in response to an interlock read command. The processors include a lockout check circuit responsive to the condition of the lockout indicator and will restrict generation of additional interlock read commands according to a predetermined access gating criterion until the lockout indicator is reset. In this manner, processor nodes of the system are assured equitable access to a memory node.
摘要翻译： 多节点计算机系统包括在挂起总线上互连的处理器节点，存储器节点和输入/输出节点。 该系统包括锁定指示器，该锁定指示器响应于互锁读取命令而从处理器节点从存储器节点接收到锁定的响应消息时被设置。 处理器包括响应于锁定指示器的状况的锁定检查电路，并且将根据预定的访问选通标准限制产生额外的互锁读取命令，直到锁定指示器被复位。 以这种方式，系统的处理器节点被确保公平地访问存储器节点。
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公开(公告)号：US5829051A
公开(公告)日：1998-10-27
申请号：US223069
申请日：1994-04-04
CPC分类号： G06F12/0864
摘要： An apparatus for allocating data to and retrieving data from a cache includes a memory subsystem coupled between a processor and a memory to provide quick access of memory data to the processor. The memory subsystem includes a cache memory. The address provided to the memory subsystem is divided into a cache index and a tag, and the cache index is hashed to provide a plurality of alternative addresses for accessing the cache. During a cache read, each of the alternative addresses are selected to search for the data responsive to an indicator of the validity of the data at the locations. The selection of the alternative address may be done through a mask having a number of bits corresponding to the number of alternative addresses. Each bit indicates whether the alternative address at that location should be used during the access of the cache in search of the data. Alternatively, a memory device which has more entries than the cache has blocks may be used to store the select value of the best alternative address to use to locate the data. Data is allocated to each alternative address based upon a modified least recently used technique wherein a quantum number and modula counter are used to time stamp the data.
摘要翻译： 一种用于向高速缓存提供数据并从其中检索数据的装置包括耦合在处理器和存储器之间的存储器子系统，以便将存储器数据快速地存取到处理器。 存储器子系统包括高速缓冲存储器。 提供给存储器子系统的地址被划分为高速缓存索引和标签，并且高速缓存索引被散列以提供用于访问高速缓存的多个替代地址。 在缓存读取期间，选择每个备选地址以响应于在该位置处的数据的有效性的指示符来搜索数据。 替代地址的选择可以通过具有对应于替代地址的数量的位数的掩码来完成。 每个位指示在缓存访问期间是否应该使用该位置处的替代地址来搜索数据。 或者，具有比高速缓存具有更多条目的存储器装置可以用于存储用于定位数据的最佳替代地址的选择值。 基于修改的最近最少使用的技术将数据分配给每个备选地址，其中使用量子数和模数计数器来对数据进行时间戳。
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17.发明授权Method for error recovery spinlock in asymmetrically accessed multiprocessor shared memory 失效在不对称访问的多处理器共享存储器中的错误恢复自旋锁的方法
公开(公告)号：US5924122A
公开(公告)日：1999-07-13
申请号：US818757
申请日：1997-03-14
CPC分类号： H04L29/06 , H04L69/324
摘要： An error recovery method and apparatus has specific application in a networking arrangement having a plurality of individual processing nodes which communicate via shared memory space. For error recovery, the system uses a reliable error count, the value of which is maintained by all of the nodes. When an error is detected, the error count is incremented, and all of the active nodes are provided with the new error count. Any of the nodes can run the error recovery method, and may gain exclusive access to the network by acquiring an error recovery spinlock. Once the spinlock is acquired, the node holding the spinlock increments the error count and confirms that all active nodes have received the new error count. The spinlock is thereafter released.
摘要翻译： 一种错误恢复方法和装置在具有通过共享存储器空间通信的多个单独处理节点的网络布置中具有特定应用。 对于错误恢复，系统使用可靠的错误计数，其值由所有节点维护。 当检测到错误时，错误计数增加，并且所有活动节点都被提供新的错误计数。 任何节点都可以运行错误恢复方法，并可以通过获取错误恢复自旋锁来获得对网络的独占访问权限。 一旦获得了自旋锁，则保持自旋锁的节点会增加错误计数，并确认所有活动节点已收到新的错误计数。 螺旋锁随后释放。
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18.发明授权Method and apparatus for managing multiple lock indicators in a multiprocessor computer system 失效用于在多处理器计算机系统中管理多个锁定指示器的方法和装置
公开(公告)号：US5068781A
公开(公告)日：1991-11-26
申请号：US372565
申请日：1989-06-28
CPC分类号： G06F9/52 , G06F13/4217
摘要： A computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to a memory or I/O node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processes in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the memory which indicates that the specified location is locked.
摘要翻译： 具有通过挂起总线互连的多个处理器的计算机系统提供采用多个锁定位的独占读取 - 修改 - 写入操作。 处理器产生互锁读命令，该命令作为通过挂起总线的传送被传送到存储器或I / O节点。 在处理器传输的每个总线周期之后，确认确认由存储器发送回处理器两个总线周期。 处理器传输（包括互锁读取命令）存储在存储器中的输入队列中，并依次由存储器进行处理。 对指定的存储器位置的第一联锁读取命令导致为该位置设置锁定位，以及包括要由存储器生成并存储在输出队列中的指定位置的内容的第一类型的响应消息。 存储器通过仲裁处理获得对待处理总线的访问，并且在启动互锁读取命令之后的未指定时间发送包括在联锁读取命令中指定的存储器位置的内容的响应消息。 从处理器到相同存储器位置的随后的互锁读取命令将导致拒绝对指定位置的访问以及存储器生成指示指定位置被锁定的第二类型的响应消息。
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19.发明授权公开(公告)号：US06295585B1
公开(公告)日：2001-09-25
申请号：US08482925
申请日：1995-06-07
IPC分类号： G06F1314
CPC分类号： G06F9/544
摘要： A multi-node computer network includes a plurality of nodes coupled together via a data link. Each of the nodes includes a local memory, which further comprises a shared memory. Certain items of data that are to be shared by the nodes are stored in the shared portion of memory. Associated with each of the shared data items is a data structure. When a node sharing data with other nodes in the system seeks to modify the data, it transmits the modifications over the data link to the other nodes in the network. Each update is received in order by each node in the cluster. As part of the last transmission by the modifying node, an acknowledgement request is sent to the receiving nodes in the cluster. Each node that receives the acknowledgment request returns an acknowledgement to the sending node. The returned acknowledgement is written to the data structure associated with the shared data item. If there is an error during the transmission of the message, the receiving node does not transmit an acknowledgement, and the sending node is thereby notified that an error has occurred.
摘要翻译： 多节点计算机网络包括通过数据链路耦合在一起的多个节点。 每个节点包括本地存储器，其还包括共享存储器。 要由节点共享的某些数据项存储在存储器的共享部分中。 与每个共享数据项相关联的是数据结构。 当与系统中的其他节点共享数据的节点寻求修改数据时，它将数据链路上的修改发送到网络中的其他节点。 群集中的每个节点按顺序接收每个更新。 作为修改节点的最后一次传输的一部分，向群集中的接收节点发送确认请求。 接收确认请求的每个节点向发送节点返回确认。 返回的确认被写入与共享数据项相关联的数据结构。 如果在消息的发送期间存在错误，则接收节点不发送确认，并且由此通知发送节点发生了错误。
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公开(公告)号：US5426741A
公开(公告)日：1995-06-20
申请号：US182531
申请日：1994-01-14
CPC分类号： G06F11/348 , G06F11/349 , G06F11/3409 , G06F11/3495 , G06F2201/86 , G06F2201/88
摘要： A monitor for monitoring the occurrence of events on the bus (15) of a multiprocessor computer system. The bus event monitor (BEM) includes a dedicated BEM processor (23) and an event counter subsystem (25). During each bus cycle, the BEM (21) captures and interprets the packet of data being transmitted on the bus (15). If the packet represents an event designated by the user to be of interest, a counter associated with the type of packet that was captured and interpreted is incremented by one. More specifically, a field programmable gate array (FPGA), configured by the user, defines the type of events to be counted. When an event to be accounted occurs, the FPGA (33) produces a counter address that is based on the nature of the event, and causes an enable pulse to be generated. The address is applied to the active one of two event counter banks (39a, 39b) via an input crossbar switch (37a). The enable pulse enables the addressed event counter to be incremented by one. The inactive counter bank is available for reading by the dedicated BEM processor (23) while the counters of the active counter bank are being incremented. Preferably, each counter bank contains a large number of counters (e.g., 64K), each having a large capacity (e.g., 32 bit). As a result, a large number of different events can be counted over an indefinitely long period of time.
摘要翻译： 一种用于监视多处理器计算机系统的总线（15）上的事件发生的监视器。 总线事件监视器（BEM）包括专用BEM处理器（23）和事件计数器子系统（25）。 在每个总线周期期间，BEM（21）捕获并解释正在总线（15）上发送的数据的分组。 如果分组表示由用户指定为感兴趣的事件，则与捕获和解释的分组类型相关联的计数器增加1。 更具体地，由用户配置的现场可编程门阵列（FPGA）定义要计数的事件的类型。 当要考虑的事件发生时，FPGA（33）产生基于事件性质的计数器地址，并且产生使能脉冲。 通过输入交叉开关（37a）将地址应用于两个事件计数器组（39a，39b）中的活动的一个。 使能脉冲使寻址的事件计数器增加1。 当活动计数器组的计数器递增时，非活动计数器存储体可供专用BEM处理器（23）读取。 优选地，每个计数器存储体包含大量的计数器（例如，64K），每个计数器具有大容量（例如，32位）。 因此，大量不同的事件可以无限期地计算在一起。
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