公开(公告)号：US20070071155A1

公开(公告)日：2007-03-29

申请号：US11236834

申请日：2005-09-27

申请人： David Boerstler ,  Matthew Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Riley

发明人： David Boerstler ,  Matthew Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Riley

IPC分类号： H04B17/00 ,  H03D3/24

CPC分类号： G06F1/10 ,  H03L7/095

摘要： An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.

摘要翻译： 公开了一种包括频率合成器锁定检测系统的信息处理系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。 分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。 锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。 以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

公开(公告)号：US20060212739A1

公开(公告)日：2006-09-21

申请号：US11082973

申请日：2005-03-17

申请人： David Boerstler ,  Eskinder Hailu ,  Byron Krauter ,  Kazuhiko Miki ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Byron Krauter ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： G06F1/04

CPC分类号： G06F1/10 ,  H03K5/1565

摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

摘要翻译： 提供了一种方法，装置和计算机程序来测量和/或校正占空比。 各种信号的占空比，特别是时钟信号是很重要的。 然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。 为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。

公开(公告)号：US20060190746A1

公开(公告)日：2006-08-24

申请号：US11065549

申请日：2005-02-24

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G06F1/26

CPC分类号： G06F1/26

摘要： A system and system for automatic voltage calibration is presented. A voltage calibration system includes three main units, which are a voltage level trimming unit, a trim detection unit, and a trim control unit. The three units work in conjunction with each other during a trimming operation in order to identify a tap voltage that is closest to a target voltage. In one embodiment, the voltage calibration system may be used to calibrate a voltage regulator. Upon commencement of calibration, the voltage regulator's feedback loop is open, and the target voltage is selected as the input for the feedback port of the amplifier. The voltage regulator serves as a voltage comparator that compares each tap voltage to the target voltage. When the calibration is complete, regulator's feedback loop is closed and the closest tap voltage to the target voltage is used as the regulator's input.

摘要翻译： 提出了一种用于自动电压校准的系统和系统。 电压校准系统包括三个主要单元，它们是电压调整单元，微调检测单元和微调控制单元。 三个单元在微调操作期间相互协调工作，以便识别最接近目标电压的抽头电压。 在一个实施例中，电压校准系统可用于校准电压调节器。 校准开始后，电压调节器的反馈回路打开，目标电压被选为放大器反馈端口的输入。 电压调节器用作将每个抽头电压与目标电压进行比较的电压比较器。 当校准完成时，调节器的反馈回路闭合，并将最接近目标电压的分接电压用作调节器的输入。

公开(公告)号：US20060091965A1

公开(公告)日：2006-05-04

申请号：US10981155

申请日：2004-11-04

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03L7/00

CPC分类号： H03L7/0893 ,  H03L7/093 ,  H03L7/095

摘要： A method, an apparatus, and a computer program are provided to minimize filter capacitor leakage in a Phased Locked Loop (PLL). In high frequency processors and devices, filter leakage currents can cause substantial problems by causing PLLs to drift out of phase lock. To combat the leakage currents, a dummy filter and other components are employed to provide additional charge or voltage to a low pass filter during lock. The provision of the charge or voltage exponentially decreases the rate of decay of voltage across the low pass filter caused by leakage currents.

摘要翻译： 提供了一种方法，装置和计算机程序以最小化相位锁定环（PLL）中的滤波电容器泄漏。 在高频处理器和器件中，滤波器漏电流可能会导致相位锁相位漂移出现相当大的问题。 为了防止泄漏电流，使用虚拟滤波器和其他组件在锁定期间向低通滤波器提供额外的充电或电压。 充电或电压的提供以指数方式降低由漏电流引起的低通滤波器的电压衰减速率。

公开(公告)号：US20060069929A1

公开(公告)日：2006-03-30

申请号：US10955121

申请日：2004-09-30

申请人： David Boerstler ,  Eskinder Hailu ,  Mack Riley ,  Michael Wang

发明人： David Boerstler ,  Eskinder Hailu ,  Mack Riley ,  Michael Wang

IPC分类号： G06F1/26

CPC分类号： G06F1/26

摘要： The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.

摘要翻译： 本发明提供了一种用于转换时钟速度的电路。 计数器耦合到计时装置。 比较器耦合到计数器的输出端。 第一分频器耦合到计数器的输出端。 处理器装置耦合到第一分频器的输出，从而减小电流浪涌。

公开(公告)号：US20050280406A1

公开(公告)日：2005-12-22

申请号：US10870533

申请日：2004-06-17

申请人： David Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki

发明人： David Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki

IPC分类号： G06F19/00 ,  H03L7/093

CPC分类号： H03L7/093

摘要： The present invention provides a method, apparatus, and computer program for measuring the current leakage in a Low Pass Filter (LPF) capacitor of a Phased Locked Loop (PLL). As a result of thinner and thinner film capacitors in Complementary Metal-Oxide Semiconductor (CMOS) technology, leakage current, which causes a PLL to drift out of phase lock, has become an increasingly difficult problem. To overcome the leakage current problems, knowing the leakage current of an LPF capacitor is important to implement the correction circuitry. In the present invention, an external interface and a time interface analyzer are used to charge the LPF capacitor and measure the output frequency of the PLL's Voltage Controlled Oscillator. Because of the change in the output frequency, the leakage current can be determined.

摘要翻译： 本发明提供一种用于测量相位锁定环（PLL）的低通滤波器（LPF）电容器中的电流泄漏的方法，装置和计算机程序。 由于互补金属氧化物半导体（CMOS）技术中薄膜电容器越来越薄，导致PLL漂移出相位锁定的漏电流已经成为越来越难的问题。 为了克服漏电流问题，知道LPF电容器的漏电流对于实现校正电路是重要的。 在本发明中，使用外部接口和时间接口分析器对LPF电容器充电并测量PLL的压控振荡器的输出频率。 由于输出频率的变化，可以确定漏电流。

公开(公告)号：US20050040855A1

公开(公告)日：2005-02-24

申请号：US10645040

申请日：2003-08-21

申请人： David Boerstler ,  Eskinder Hailu

发明人： David Boerstler ,  Eskinder Hailu

IPC分类号： G06F1/08 ,  H03K5/135 ,  H03K17/00 ,  H03K19/00

CPC分类号： G06F1/08 ,  H03K5/135 ,  H03K17/005

摘要： A clock signal selector circuit is disclosed including a synchronizer circuit, two switching circuits, and a multiplexer. The synchronizer circuit synchronizes a first control signal to a first clock signal, thereby producing a second control signal. A first switching circuit produces the first clock signal at a first node when the second control signal is asserted. The multiplexer drives a second node with a signal at the first node when the second control signal is asserted. The second switching circuit forms an electrical connection between the first and second nodes when the second control signal is deasserted. The two switching circuits significantly reduce a probability of error at the second node due to metastability when the second control signal transitions from asserted to deasserted and the first clock signal is deselected. The second switching circuit provides electrical feedback from the second node to the first node.

摘要翻译： 公开了一种包括同步器电路，两个开关电路和多路复用器的时钟信号选择器电路。 同步器电路使第一控制信号与第一时钟信号同步，从而产生第二控制信号。 当第二控制信号被断言时，第一开关电路在第一节点处产生第一时钟信号。 当第二控制信号被断言时，多路复用器在第一节点处驱动具有信号的第二节点。 当第二控制信号被断言时，第二切换电路在第一和第二节点之间形成电连接。 当第二控制信号从被断言转变为无效并且第一时钟信号被取消选择时，两个开关电路由于亚稳定性而显着地降低了第二节点处的误差概率。 第二开关电路提供从第二节点到第一节点的电反馈。

公开(公告)号：US20070300113A1

公开(公告)日：2007-12-27

申请号：US11848314

申请日：2007-08-31

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G06F11/27

CPC分类号： H03K5/1565 ,  G01R31/31727 ,  G01R31/3187

摘要： An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance are provided. A chip level built-in circuit that automatically calibrates the duty cycle correction (DCC) circuit setting for each chip is provided. This chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. Results of a built-in self test, i.e. pass or fail, of an array are provided to the DCC circuit controller. If the result of the built-in self test is a pass, then the current DCC circuit controller's DCC control bit setting is set as the setting for the chip. If the result from the built-in self test is a fail, the DCC circuit controller's DCC control bits setting is incremented to a next setting and the self-test is performed again.

摘要翻译： 提供一种用于自动校准占空比电路以实现最大性能的装置和方法。 提供了自动校准每个芯片的占空比校正（DCC）电路设置的芯片级内置电路。 该芯片级内置电路包括时钟生成宏单元，简单占空比校正（DCC）电路，阵列片和内置自检单元以及DCC电路控制器。 向DCC电路控制器提供阵列的内置自检，即通过或失败的结果。 如果内置自检的结果是通过，则将当前DCC电路控制器的DCC控制位设置设置为芯片的设置。 如果内置自检的结果为失败，DCC电路控制器的DCC控制位设置将增加到下一个设置，并再次执行自检。

公开(公告)号：US20070266285A1

公开(公告)日：2007-11-15

申请号：US11381031

申请日：2006-05-01

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G01R31/28

CPC分类号： G01R31/31727

摘要： The disclosed methodology and apparatus measure the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.

摘要翻译： 所公开的方法和装置测量时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比。 在一个实施例中，DCM电路包括由电荷泵驱动的电容器。 参考时钟信号驱动电荷泵。 时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。 控制软件访问数据存储，以确定测试时钟信号对应的占空比。

公开(公告)号：US20070100505A1

公开(公告)日：2007-05-03

申请号：US11260570

申请日：2005-10-27

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G05D11/00

CPC分类号： G01R29/02 ,  G01R31/2884

摘要： A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.

摘要翻译： 提供了一种用于测量诸如微处理器或片上系统的集成电路器件中被测信号占空比的机构。 该机制产生与占空比成比例的频率，可以使用普通实验室或制造设备测量。 该机构可以使用标准互补金属氧化物半导体工艺中的简单电路来实现，其需要非常小的面积并且可以在不使用时关闭电源。 该机构可以包括例如低通滤波器，用于提供校准参考电压信号的分压器，电压到频率转换器，用于分频频率信号输出的分频器，使得信号的频率在预定范围内 ，以及输出驱动器和输出板。 从频率输出信号，可以使用片外设备来计算被测信号的占空比。