公开(公告)号：US20060069929A1

公开(公告)日：2006-03-30

申请号：US10955121

申请日：2004-09-30

申请人： David Boerstler ,  Eskinder Hailu ,  Mack Riley ,  Michael Wang

发明人： David Boerstler ,  Eskinder Hailu ,  Mack Riley ,  Michael Wang

IPC分类号： G06F1/26

CPC分类号： G06F1/26

摘要： The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.

摘要翻译： 本发明提供了一种用于转换时钟速度的电路。 计数器耦合到计时装置。 比较器耦合到计数器的输出端。 第一分频器耦合到计数器的输出端。 处理器装置耦合到第一分频器的输出，从而减小电流浪涌。

公开(公告)号：US20060093047A1

公开(公告)日：2006-05-04

申请号：US10981154

申请日：2004-11-04

申请人： David Boerstler ,  Eskinder Hailu ,  Mack Riley ,  Michael Wang

发明人： David Boerstler ,  Eskinder Hailu ,  Mack Riley ,  Michael Wang

IPC分类号： H04L25/00

CPC分类号： H03K23/662 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126

摘要： A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.

摘要翻译： 提供了一种方法，装置和计算机程序以减少模式转换期间的瞬态电流摆动。 传统上，芯片上的瞬态电源电压波动占大部分电源。 串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。 然而，不能实现串联电感和电阻的降低的情况。 因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。

公开(公告)号：US20070071155A1

公开(公告)日：2007-03-29

申请号：US11236834

申请日：2005-09-27

申请人： David Boerstler ,  Matthew Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Riley

发明人： David Boerstler ,  Matthew Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Riley

IPC分类号： H04B17/00 ,  H03D3/24

CPC分类号： G06F1/10 ,  H03L7/095

摘要： An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.

摘要翻译： 公开了一种包括频率合成器锁定检测系统的信息处理系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。 分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。 锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。 以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

公开(公告)号：US20070071154A1

公开(公告)日：2007-03-29

申请号：US11236658

申请日：2005-09-27

申请人： David Boerstler ,  Matthew Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Riley

发明人： David Boerstler ,  Matthew Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Riley

IPC分类号： H03D3/24

CPC分类号： H03L7/093 ,  H03L7/095

摘要： A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.

摘要翻译： 公开了一种频率合成器锁定检测系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。 分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。 锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。 以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

公开(公告)号：US20070236266A1

公开(公告)日：2007-10-11

申请号：US11278842

申请日：2006-04-06

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K3/017

CPC分类号： H03K5/1534 ,  H03K5/156 ,  H03K2005/00293

摘要： An apparatus and method for extracting a maximum pulse width of a pulse width limiter are provided. The apparatus and method of the illustrative embodiments performs such extraction using a circuit that is configured to eliminate the majority of the delay cells utilized in the circuit arrangement described in commonly assigned and co-pending U.S. patent application Ser. No. 11/109,090 (hereafter referred to as the '090 application). The elimination of these delay cells is made possible in one illustrative embodiment by replacing an OR gate in the circuit configuration of the '090 application with an edge triggered re-settable latch. The replacement of the OR gate with the edge triggered re-settable latch reduces the amount of chip area used in addition to the power consumption of the circuit.

摘要翻译： 提供了一种用于提取脉冲宽度限制器的最大脉冲宽度的装置和方法。 说明性实施例的装置和方法使用被配置为消除在共同转让和共同未决的美国专利申请Ser中描述的电路装置中使用的大多数延迟单元的电路来执行这种提取。 第11 / 109,090号（以下简称“090”）。 在一个说明性实施例中，通过用'边缘触发的可重新设定的锁存器'替换'090应用的电路配置中的或门，可以消除这些延迟单元。 利用边沿触发的可重新设置的锁存器替换或门可以减少除了电路功耗之外使用的芯片面积。

公开(公告)号：US20070126475A1

公开(公告)日：2007-06-07

申请号：US11466542

申请日：2006-08-23

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K19/173

CPC分类号： G01R31/2632

摘要： A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by hand. By employing a thermal voltage proportional to absolute temperature (PTAT) generator in conjunction with an extraction mechanism, the ideality factor can be extracted in an semi-automatic manner. Therefore, a reliable, quick, and less expensive device can be employed to improve measurements of ideality factors.

摘要翻译： 提供了一种半自动提取二极管理想因子的方法，装置和计算机程序。 传统上，二极管的电流/电压曲线为理想因素外推提供了基础，必须用手来确定。 通过采用与绝对温度（PTAT）发生器成比例的热电压与提取机制，理想因子可以半自动提取。 因此，可以采用可靠，快速和便宜的装置来改善理想因素的测量。

公开(公告)号：US20070079197A1

公开(公告)日：2007-04-05

申请号：US11242677

申请日：2005-10-04

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G01R31/28

CPC分类号： H03K5/1565 ,  G01R31/31727 ,  G01R31/3187

摘要： An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance are provided. A chip level built-in circuit that automatically calibrates the duty cycle correction (DCC) circuit setting for each chip is provided. This chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. Results of a built-in self test, i.e. pass or fail, of an array are provided to the DCC circuit controller. If the result of the built-in self test is a pass, then the current DCC circuit controller's DCC control bit setting is set as the setting for the chip. If the result from the built-in self test is a fail, the DCC circuit controller's DCC control bits setting is incremented to a next setting and the self-test is performed again.

摘要翻译： 提供一种用于自动校准占空比电路以实现最大性能的装置和方法。 提供了自动校准每个芯片的占空比校正（DCC）电路设置的芯片级内置电路。 该芯片级内置电路包括时钟生成宏单元，简单占空比校正（DCC）电路，阵列片和内置自检单元以及DCC电路控制器。 向DCC电路控制器提供阵列的内置自检，即通过或失败的结果。 如果内置自检的结果是通过，则将当前DCC电路控制器的DCC控制位设置设置为芯片的设置。 如果内置自检的结果为失败，DCC电路控制器的DCC控制位设置将增加到下一个设置，并再次执行自检。

公开(公告)号：US20060232310A1

公开(公告)日：2006-10-19

申请号：US11109090

申请日：2005-04-19

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K3/017

CPC分类号： H03K5/156 ,  G01R31/31708 ,  G01R31/31725 ,  H03K5/05 ,  H03K5/26

摘要： The present invention provides for a method for characterization of pulse-width limiter outputs. A known clock signal is received. A pulse width of the received known clock signal is limited through a first pulse-width limiter to generate a first intermediate signal. The first intermediate signal is delayed by a known amount to generate a first delayed signal. The first intermediate signal is inverted to generate a first inverted signal. A pulse width of the first inverted signal is limited through a second pulse-width limiter to generate a second intermediate signal. The second intermediate signal is delayed by a known amount to generate a second delayed signal. A logic OR operation is performed on the first delayed signal and the second delayed signal to generate a clock out signal.

摘要翻译： 本发明提供了用于表征脉冲宽度限制器输出的方法。 接收已知的时钟信号。 所接收的已知时钟信号的脉冲宽度通过第一脉冲宽度限制器来限制，以产生第一中间信号。 第一中间信号被延迟已知的量以产生第一延迟信号。 第一中间信号被反相以产生第一反相信号。 通过第二脉冲宽度限幅器限制第一反相信号的脉冲宽度以产生第二中间信号。 第二中间信号被延迟已知的量以产生第二延迟信号。 对第一延迟信号和第二延迟信号执行逻辑或运算以产生时钟输出信号。

公开(公告)号：US20050248376A1

公开(公告)日：2005-11-10

申请号：US10840562

申请日：2004-05-06

申请人： David Boerstler ,  Eskinder Hailu

发明人： David Boerstler ,  Eskinder Hailu

IPC分类号： H03L7/00 ,  H03L7/06 ,  H03L7/089 ,  H03L7/093

CPC分类号： H03L7/093 ,  H03L7/0891

摘要： The present invention provides for a low pass filter. A first capacitor, has a first associated leakage current. A second capacitor has a specified capacitance that is a fraction of the capacitance of the first capacitor, the second capacitor further having a second associated leakage current. A voltage follower circuit is coupled to the output of the first and second capacitor. First and second current sources are coupled to the voltage follower circuit. A bias current source is coupled the first current source. A current mirror is coupled to the second current source, and the current mirror is further coupled to at least the anode of the first capacitor, thereby generating replacement current of a capacitor within a low-pass filter.

摘要翻译： 本发明提供一种低通滤波器。 第一电容器具有第一相关泄漏电流。 第二电容器具有指定电容，其是第一电容器的电容的一部分，第二电容器还具有第二相关联的漏电流。 电压跟随器电路耦合到第一和第二电容器的输出。 第一和第二电流源耦合到电压跟随器电路。 偏置电流源耦合第一电流源。 电流镜耦合到第二电流源，并且电流镜还被耦合到至少第一电容器的阳极，从而产生低通滤波器内的电容器的替换电流。

公开(公告)号：US20070260409A1

公开(公告)日：2007-11-08

申请号：US11777370

申请日：2007-07-13

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G06F19/00

CPC分类号： G01R29/02 ,  G01R31/2884

摘要： A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.

摘要翻译： 提供了一种用于测量诸如微处理器或片上系统的集成电路器件中被测信号占空比的机构。 该机制产生与占空比成比例的频率，可以使用普通实验室或制造设备测量。 该机构可以使用标准互补金属氧化物半导体工艺中的简单电路来实现，其需要非常小的面积并且可以在不使用时关闭电源。 该机构可以包括例如低通滤波器，用于提供校准参考电压信号的分压器，电压到频率转换器，用于分频频率信号输出的分频器，使得信号的频率在预定范围内 ，以及输出驱动器和输出板。 从频率输出信号，可以使用片外设备来计算被测信号的占空比。