公开(公告)号：US20080104550A1

公开(公告)日：2008-05-01

申请号：US11537390

申请日：2006-09-29

Applicant: Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

Inventor： Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.

Abstract translation: 一种方法包括接收与集成电路装置相关联的设计数据。 集成电路装置包括具有限定在其中的角部的第一元件和与第一元件重叠的第二元件。 基于第二元件和拐角之间的距离来调整为设计数据中的第一元件指定的尺寸。 基于经调整的尺寸模拟集成电路器件。

公开(公告)号：US5970353A

公开(公告)日：1999-10-19

申请号：US050730

申请日：1998-03-30

Applicant: Akif Sultan

Inventor： Akif Sultan

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L29/6656 ,  H01L29/7836 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586

Abstract: A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56). Lastly, the method includes thermally treating the substrate (56), wherein the interstitials (62) enhance a lateral diffusion (84) under the gate oxide (54) without substantially impacting a vertical diffusion (86) of the extension regions (66, 67), thereby reducing the effective channel length without an increase in a junction depth of the drain (70) and the drain extension region (66) or the source (72) and the source extension region (67).

公开(公告)号：US20090090969A1

公开(公告)日：2009-04-09

申请号：US11867743

申请日：2007-10-05

Applicant: Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

Inventor： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

Abstract translation: 第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。 第一晶体管的电压阈值基于第一偏置电荷。 第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。 第二晶体管的电压阈值基于第二偏置电荷。

公开(公告)号：US06365516B1

公开(公告)日：2002-04-02

申请号：US09483081

申请日：2000-01-14

Applicant: Austin Frenkel ,  Akif Sultan ,  Paul Besser

Inventor： Austin Frenkel ,  Akif Sultan ,  Paul Besser

IPC: H01L2144

CPC classification number: H01L21/0206 ,  H01L21/28518

Abstract: Various methods of fabricating a silicide structure are provided. In one aspect, a method of fabricating a circuit structure on a silicon surface is provided that includes exposing the silicon surface to a plasma ambient containing hydrogen and an inert gas, and depositing a metallic material capable of forming silicide on the silicon surface. The metallic material is heated to form a metal silicide on the silicon surface. The method provides for low sheet resistance silicide structures by eliminating native oxide films without the risk of spacer material backsputtering.

Abstract translation: 提供了制造硅化物结构的各种方法。 一方面，提供一种在硅表面上制造电路结构的方法，其包括将硅表面暴露于含有氢气和惰性气体的等离子体环境中，以及在硅表面上沉积能够形成硅化物的金属材料。 金属材料被加热以在硅表面上形成金属硅化物。 该方法通过消除天然氧化物膜而不会产生间隔材料反溅镀的风险，从而提供低电阻硅化物结构。

公开(公告)号：US06346463B1

公开(公告)日：2002-02-12

申请号：US09565858

申请日：2000-05-05

Applicant: Akif Sultan ,  Frederick N. Hause

Inventor： Akif Sultan ,  Frederick N. Hause

IPC: H01L2104

CPC classification number: H01L29/1079 ,  H01L21/26513 ,  H01L21/823493

Abstract: A method for forming a semiconductor device is provided. A base layer is provided. A first epitaxial layer having a first dopant at a first concentration is formed above the base layer. A second epitaxial layer having a second dopant at a second concentration is formed above the first epitaxial layer. The second concentration is greater than the first concentration. A third epitaxial layer having a third dopant at a third concentration is formed above the second epitaxial layer. The third concentration is less than the second concentration. Ions are implanted in the third epitaxial layer to form an implant region. The implant region is in contact with the second epitaxial layer. A semiconductor device comprises a base layer, first, second, and third epitaxial layers, and an implant region. The first epitaxial layer has a first dopant at a first concentration disposed above the base layer. The second epitaxial layer has a second dopant at a second concentration disposed above the first epitaxial layer. The second concentration is greater than the first concentration. The third epitaxial layer has a third dopant at a third concentration disposed above the second epitaxial layer. The third concentration is less than the second concentration. The implant region is defined in the third epitaxial layer and is in contact with the second epitaxial layer.

Abstract translation: 提供一种形成半导体器件的方法。 提供基层。 具有第一浓度的第一掺杂剂的第一外延层形成在基层之上。 具有第二浓度的第二掺杂剂的第二外延层形成在第一外延层的上方。 第二浓度大于第一浓度。 具有第三浓度的第三掺杂剂的第三外延层形成在第二外延层的上方。 第三浓度小于第二浓度。 将离子注入第三外延层以形成植入区。 注入区域与第二外延层接触。 半导体器件包括基极层，第一，第二和第三外延层以及植入区域。 第一外延层具有设置在基极层之上的第一浓度的第一掺杂剂。 第二外延层具有设置在第一外延层上方的第二浓度的第二掺杂剂。 第二浓度大于第一浓度。 第三外延层具有设置在第二外延层上方的第三浓度的第三掺杂剂。 第三浓度小于第二浓度。 注入区域限定在第三外延层中并且与第二外延层接触。

公开(公告)号：US6063682A

公开(公告)日：2000-05-16

申请号：US49322

申请日：1998-03-27

Applicant: Akif Sultan ,  Geoffrey Choh-Fei Yeap

Inventor： Akif Sultan ,  Geoffrey Choh-Fei Yeap

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/2652 ,  Y10S438/918

Abstract: A method of fabricating a transistor is provided. According to the method, a heavy ion is implanted into a silicon substrate so as to amorphize at least a portion of the silicon substrate. The amorphized silicon is substantially free of channels. A dopant is subsequently implanted into the amorphized silicon, and the amorphized silicon substantially contains the implanted dopant. Thereafter, a silicon implanting step is performed to create an excess of vacancies to interstitials within a predetermined range. Enhanced diffusion of the dopant within the predetermined range is mitigated because of the excess of vacancies to interstitials within this predetermined range.

Abstract translation: 提供一种制造晶体管的方法。 根据该方法，将重离子注入到硅衬底中，以使至少一部分硅衬底非晶化。 非晶化硅基本上不含通道。 随后将掺杂剂注入到非晶化硅中，并且非晶化硅基本上包含注入的掺杂剂。 此后，进行硅注入步骤以在预定范围内产生过多的间隙空隙。 由于在该预定范围内间隙的空位过多，掺杂剂在预定范围内的增强扩散减轻。

公开(公告)号：US08361870B2

公开(公告)日：2013-01-29

申请号：US12843350

申请日：2010-07-26

Applicant: Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

Inventor： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract translation: 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。

公开(公告)号：US20120003802A1

公开(公告)日：2012-01-05

申请号：US13230083

申请日：2011-09-12

Applicant: Jian Chen ,  James F. Buller ,  Akif Sultan

Inventor： Jian Chen ,  James F. Buller ,  Akif Sultan

IPC: H01L21/336

CPC classification number: H01L29/78618 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7848

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract translation: 本发明涉及具有不对称硅锗源区的晶体管及其制造方法。 在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区 基质。

公开(公告)号：US08035098B1

公开(公告)日：2011-10-11

申请号：US11278618

申请日：2006-04-04

Applicant: Jian Chen ,  James F. Buller ,  Akif Sultan

Inventor： Jian Chen ,  James F. Buller ,  Akif Sultan

IPC: H01L29/06 ,  H01L21/336

CPC classification number: H01L29/78618 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7848

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract translation: 本发明涉及具有不对称硅锗源区的晶体管及其制造方法。 在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区 基质。

公开(公告)号：US07793240B2

公开(公告)日：2010-09-07

申请号：US11537390

申请日：2006-09-29

Applicant: Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

Inventor： Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.

Abstract translation: 一种方法包括接收与集成电路装置相关联的设计数据。 集成电路装置包括具有限定在其中的角部的第一元件和与第一元件重叠的第二元件。 基于第二元件和拐角之间的距离来调整为设计数据中的第一元件指定的尺寸。 基于经调整的尺寸模拟集成电路器件。