公开(公告)号：US07206366B2

公开(公告)日：2007-04-17

申请号：US10337567

申请日：2003-01-07

Applicant: Ichiro Fujimori ,  Davide Tonietto

Inventor： Ichiro Fujimori ,  Davide Tonietto

IPC: H04B1/10 ,  H03H7/30 ,  H03D1/00 ,  G11B5/02

CPC classification number: H04B10/291

Abstract: Aspects of the invention may provide a method and system for adjusting a gain and/or a frequency response of an input signal for a multimode PHY device. A signal divider may apportion the input signal into a gain adjustment signal and/or an equalization adjustment signal upon receipt of the input signal. A signal adjuster coupled to the signal divider may adjust a gain of the apportioned gain adjustment signal within the multimode PHY device. An equalizer coupled to the signal divider may be configured to equalize the equalization adjustment signal within the multimode PHY device. A summer coupled to the equalizer and signal adjuster may be adapted to sum the adjusted adjustment signal and the equalized equalization adjustment signal within the multimode PHY device to create an output equalized signal having a desired gain and/or frequency response.

Abstract translation: 本发明的各方面可以提供用于调整多模PHY设备的输入信号的增益和/或频率响应的方法和系统。 信号分配器可以在接收到输入信号时将输入信号分配成增益调整信号和/或均衡调整信号。 耦合到信号分配器的信号调节器可以调整多模PHY器件内的分配增益调整信号的增益。 耦合到信号分配器的均衡器可以被配置为均衡多模PHY设备内的均衡调整信号。 耦合到均衡器和信号调节器的加法器可以适于将经调整的调整信号和多模PHY装置内的均衡均衡调整信号相加以产生具有期望增益和/或频率响应的输出均衡信号。

公开(公告)号：US09553600B1

公开(公告)日：2017-01-24

申请号：US15187161

申请日：2016-06-20

Applicant: Marc-Andre Lacroix ,  Henry Wong ,  Davide Tonietto

Inventor： Marc-Andre Lacroix ,  Henry Wong ,  Davide Tonietto

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/00 ,  H04L7/00

CPC classification number: H03M1/0624 ,  G06F1/10 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225 ,  H04L7/0008

Abstract: The present disclosure provides a system, circuit, and method for correcting clock skew in time-interleaved analog-to-digital converters. At least two clock signals are received along respective channels. A delay of a first channel, carrying a first clock signal, is accounted for by applying one or more first adjustment factors to the channels until an edge of the first clock signal is aligned with a transition point of a reference signal. The first clock signal is swapped to the second channel, and vice-versa. A value of the reference signal as sampled by the first clock signal is compared to values of the reference signal as sampled by the second clock signal to determine a skew of the second channel vis-à-vis the first channel, and one or more second adjustment factors are applied to the second channel based on the determined skew of the second channel.

Abstract translation: 本公开提供了一种用于校正时间交织的模数转换器中的时钟偏移的系统，电路和方法。 沿相应的通道接收至少两个时钟信号。 通过对通道应用一个或多个第一调整因子直到第一时钟信号的边沿与参考信号的转换点对准来考虑承载第一时钟信号的第一通道的延迟。 第一个时钟信号被交换到第二个信道，反之亦然。 将由第一时钟信号采样的参考信号的值与由第二时钟信号采样的参考信号的值进行比较，以确定第二信道相对于第一信道的偏斜，以及一个或多个第二信道 基于确定的第二通道的倾斜度，将调整因子应用于第二通道。

公开(公告)号：US08265132B2

公开(公告)日：2012-09-11

申请号：US12419100

申请日：2009-04-06

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H03K5/159

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface module includes a line side interface, a board side interface, and a signal conditioning circuit. The line side interface includes a media coupler that receives the line side media, such as copper media or optical media. The board side interface couples the high-speed serial bit stream interface module to the PCB. A signal conditioning circuit communicatively couples to the line side interface and to the board side interface. The signal conditioning circuit receives an RX signal from the line side interface, conditions the RX signal, and provides the RX signal to the board side interface. The signal conditioning circuit receives a TX signal from the board side interface, conditions the TX signal, and provides the TX signal to the board side interface.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速位流接口模块包括线路侧接口，电路板侧接口和信号调理电路。 线路侧接口包括接收线路侧介质的介质耦合器，例如铜介质或光学介质。 板侧接口将高速串行比特流接口模块耦合到PCB。 信号调理电路通信耦合到线路侧接口和电路板侧接口。 信号调理电路从线路侧接口接收RX信号，对RX信号进行调节，并将接收信号提供给电路板侧接口。 信号调理电路从电路板侧接口接收TX信号，调节TX信号，并向板侧接口提供TX信号。

公开(公告)号：US07733998B2

公开(公告)日：2010-06-08

申请号：US11695405

申请日：2007-04-02

Applicant: Ichiro Fujimori ,  Davide Tonietto

Inventor： Ichiro Fujimori ,  Davide Tonietto

IPC: H04B1/10

CPC classification number: H04B10/291

Abstract: Aspects of the invention may provide a method and system for adjusting a gain and/or a frequency response of an input signal for a multimode PHY device. A signal divider (704) may apportion the input signal into a gain adjustment signal and/or an equalization adjustment signal upon receipt of the input signal. A signal adjuster (702) coupled to the signal divider (704) may adjust a gain of the apportioned gain adjustment signal within the multimode PHY device (130). An equalizer (706) coupled to the signal divider (704) may be configured to equalize the equalization adjustment signal within the multimode PHY device (130). A summer (708) coupled to the equalizer (706) and signal adjuster (702) may be adapted to sum the adjusted adjustment signal and the equalized equalization adjustment signal within the multimode PHY device (130) to create an output equalized signal (712) having a desired gain and/or frequency response.

Abstract translation: 本发明的各方面可以提供用于调整多模PHY设备的输入信号的增益和/或频率响应的方法和系统。 信号分配器（704）可以在接收到输入信号时将输入信号分配成增益调整信号和/或均衡调整信号。 耦合到信号分配器（704）的信号调节器（702）可以调整多模PHY设备（130）内的分配增益调整信号的增益。 耦合到信号分配器（704）的均衡器（706）可以被配置为均衡多模PHY设备（130）内的均衡调整信号。 耦合到均衡器（706）和信号调节器（702）的加法器（708）可以适于将经调整的调整信号和多模PHY装置（130）内的均衡均衡调整信号相加，以产生输出均衡信号（712） 具有期望的增益和/或频率响应。

公开(公告)号：US20100097087A1

公开(公告)日：2010-04-22

申请号：US12254397

申请日：2008-10-20

Applicant: John Hogeboom ,  Davide Tonietto

Inventor： John Hogeboom ,  Davide Tonietto

IPC: G01R31/3187

CPC classification number: G01R31/31711

Abstract: A built-in self test for receiver operation is provided through a testing method that evaluates characteristics of a received signal eye diagram. The receiver receives a serial data signal and applies compensation to that received serial data signal to generate a compensated serial data signal. The properties of an eye diagram associated with the compensated serial data signal are measured. In this context, certain desired eye diagram properties are characterized by parameters indicative of pass/fail criteria for receiver testing. The measured eye diagram properties are then compared against the parameters. A receiver testing conclusion signal is then output based on results of the comparison.

Abstract translation: 通过一种评估接收信号眼图特性的测试方法，提供内置的接收机操作自检。 接收器接收串行数据信号并对接收到的串行数据信号进行补偿以产生经补偿的串行数据信号。 测量与补偿的串行数据信号相关联的眼图的属性。 在这种情况下，某些所需的眼图属性的特征在于指示接收机测试的通过/不合格标准的参数。 然后将测量的眼图特性与参数进行比较。 然后根据比较结果输出接收机测试结论信号。

公开(公告)号：US06351186B1

公开(公告)日：2002-02-26

申请号：US09564060

申请日：2000-05-03

Applicant: Paolo Cusinato ,  Gabriele Gandolfi ,  Vlttorio Colonna ,  Davide Tonietto

Inventor： Paolo Cusinato ,  Gabriele Gandolfi ,  Vlttorio Colonna ,  Davide Tonietto

IPC: H03F345

CPC classification number: H03F3/45273 ,  H03F3/3028 ,  H03F3/45264

Abstract: The invention relates to a Class AB operational amplifier providing both output gain enhancement and adaptative output bias. The operational amplifier includes first and second output terminals; a main differential stage having first and second differential inputs and a first differential output stage; a first adaptatively biased, boosted output stage coupling the first differential output stage to the output terminal. Each output stage includes a first NMOS output transistor having a control terminal, a first terminal coupled to the respective output terminal, and a second terminal, and includes a first output amplifier having a first input coupled to the second terminal of the first output transistor, a second input coupled to the first differential output stage to provide adaptative bias for the first boosted output stage, and an output coupled to the control terminal of the first output transistor.

Abstract translation: 本发明涉及一种提供输出增益增强和适应性输出偏置的AB类运算放大器。 运算放大器包括第一和第二输出端子; 主差分级具有第一和第二差分输入和第一差分输出级; 将第一差分输出级耦合到输出端的第一适应偏置的升压输出级。 每个输出级包括具有控制端的第一NMOS输出晶体管，耦合到相应的输出端的第一端和第二端，并且包括具有耦合到第一输出晶体管的第二端的第一输入的第一输出放大器， 耦合到所述第一差分输出级以提供所述第一升压输出级的适应偏置的第二输入以及耦合到所述第一输出晶体管的所述控制端的输出。

公开(公告)号：US10483343B2

公开(公告)日：2019-11-19

申请号：US15625731

申请日：2017-06-16

Applicant: Euhan Chong ,  Davide Tonietto ,  Zhonggui Xiang

Inventor： Euhan Chong ,  Davide Tonietto ,  Zhonggui Xiang

IPC: H01L49/02 ,  H01L23/00 ,  H04B5/00

Abstract: A device includes a first inductor positioned on a first substrate. The first inductor has at least one turn in a plane that is perpendicular to a plane of the first substrate. The first inductor is positioned for near field coupling with a second inductor. The second inductor is positioned on a second substrate, with at least one turn that is in a plane perpendicular to a plane of the second substrate. The second inductor is substantially parallel to the first inductor. Such an arrangement may be used for near field coupling, including edge-to-edge coupling, between two integrated circuits.

公开(公告)号：US09515785B2

公开(公告)日：2016-12-06

申请号：US14567068

申请日：2014-12-11

Applicant: Davide Tonietto ,  Henry Wong

Inventor： Davide Tonietto ,  Henry Wong

IPC: H04B3/46 ,  H04B17/00 ,  H04L1/20 ,  H04L27/01 ,  H04L7/00

CPC classification number: H04L1/20 ,  H04L7/0033 ,  H04L27/01

Abstract: Apparatus and methods are taught for quickly determining whether a Loss of Signal (LOS) condition has occurred for a receiver which includes an internal reference clock, a LOS circuit and a Clock and Data Recovery (CDR) circuit. The CDR circuit recovers the clock and data of an incoming signal. However, the LOS circuit can determine whether a received incoming signal includes an active signal, independent of said CDR circuit such that it samples said incoming signal utilizing said internal reference clock to determine a loss of signal prior to said CDR recovering the clock of said incoming signal. The LOS circuit includes an analog voltage threshold stage which samples the incoming signal, and produces at least one sample stream indicative of transitions in the incoming signal. The LOS circuit further includes a digital transition stage which counts transitions in order to discriminate between an active signal and noise.

Abstract translation: 教导了用于快速确定对于包括内部参考时钟，LOS电路和时钟和数据恢复（CDR）电路的接收机是否已经发生信号丢失（LOS）条件的装置和方法。 CDR电路恢复输入信号的时钟和数据。 然而，LOS电路可以确定接收到的输入信号是否包括有效信号，独立于所述CDR电路，使得其利用所述内部参考时钟采样所述输入信号，以在所述CDR恢复所述输入的时钟之前确定信号丢失 信号。 LOS电路包括模拟电压阈值级，其对输入信号进行采样，并产生指示输入信号中的转换的至少一个采样流。 LOS电路还包括数字转换级，其对转换进行计数，以便区分有效信号和噪声。

公开(公告)号：US20160173240A1

公开(公告)日：2016-06-16

申请号：US14567068

申请日：2014-12-11

Applicant: Davide Tonietto ,  Henry Wong

Inventor： Davide Tonietto ,  Henry Wong

IPC: H04L1/20 ,  H04L27/01 ,  H04L12/26

CPC classification number: H04L1/20 ,  H04L7/0033 ,  H04L27/01

Abstract: Apparatus and methods are taught for quickly determining whether a Loss of Signal (LOS) condition has occurred for a receiver which includes an internal reference clock, a LOS circuit and a Clock and Data Recovery (CDR) circuit. The CDR circuit recovers the clock and data of an incoming signal. However, the LOS circuit can determine whether a received incoming signal includes an active signal, independent of said CDR circuit such that it samples said incoming signal utilizing said internal reference clock to determine a loss of signal prior to said CDR recovering the clock of said incoming signal. The LOS circuit includes an analog voltage threshold stage which samples the incoming signal, and produces at least one sample stream indicative of transitions in the incoming signal. The LOS circuit further includes a digital transition stage which counts transitions in order to discriminate between an active signal and noise.

Abstract translation: 教导了用于快速确定对于包括内部参考时钟，LOS电路和时钟和数据恢复（CDR）电路的接收机是否已经发生信号丢失（LOS）条件的装置和方法。 CDR电路恢复输入信号的时钟和数据。 然而，LOS电路可以确定接收到的输入信号是否包括有效信号，独立于所述CDR电路，使得其利用所述内部参考时钟采样所述输入信号，以在所述CDR恢复所述输入的时钟之前确定信号丢失 信号。 LOS电路包括模拟电压阈值级，其对输入信号进行采样，并产生指示输入信号中的转换的至少一个采样流。 LOS电路还包括数字转换级，其对转换进行计数，以便区分有效信号和噪声。

公开(公告)号：US08228972B2

公开(公告)日：2012-07-24

申请号：US12132923

申请日：2008-06-04

Applicant: Davide Tonietto ,  John Hogeboom

Inventor： Davide Tonietto ,  John Hogeboom

IPC: H04B1/38

CPC classification number: H04L25/03343 ,  H04L1/205 ,  H04L1/243 ,  H04L2025/03356

Abstract: A first device transmits data over a first branch of a communications link toward a second device. That second device loops the received data pattern back over a second branch of the communications link. A bit error rate of the looped back data pattern is determined and a pre-emphasis applied to the transmitted data pattern is adjusted in response thereto. The first device further perturbs the data pattern communications signal so as to increase the bit error rate. The pre-emphasis is adjusted so as to reduce the determined bit error rate in the looped back data pattern in the presence of the perturbation. The steps for perturbing the signal and adjusting the pre-emphasis are iteratively performed, with the perturbation of the signal increasing with each iteration and adjustment of the pre-emphasis being refined with each iteration. The signal is perturbing by injecting modulation jitter into the signal (increasing each iteration) and adjusting amplitude of the signal (decreasing each iteration).

Abstract translation: 第一设备通过通信链路的第一分支向第二设备发送数据。 该第二设备将所接收的数据模式循环通过通信链路的第二分支。 确定环回数据模式的误码率，并响应于此来调整应用于发送数据模式的预加重。 第一设备进一步扰乱数据模式通信信号，以增加误码率。 调整预加重，以便在存在扰动的情况下减少确定的循环数据模式中的误码率。 迭代地执行用于干扰信号和调整预加重的步骤，随着每个迭代的信号的扰动增加，并且每次迭代改进预加重的调整。 该信号通过将调制抖动注入到信号（增加每次迭代）并调整信号的幅度（每次迭代减少）来扰乱。