Abstract:
Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
Abstract:
Systems and methods of sharing processing resources in a multi-threading environment are disclosed. An exemplary method may include allocating a lock value for a resource lock, the lock value corresponding to a state of the resource lock. A first thread may yield at least a portion of the processing resources for another thread. The resource lock may be acquired for the first thread if the lock value indicates the resource lock is available.
Abstract:
Systems, methodologies, media, and other embodiments associated with activity factor based design are described. One exemplary system embodiment includes an activity factor logic configured to determine an activity factor for a first node. The activity factor relates an input activity for the first node to an output activity for the first node. The example system may also include a transmission factor logic configured to determine a transmission factor for the first node. The transmission factor describes a degree of causal power switching between the first node and a second node. The example system may also include a downstream power logic operably connected to the activity factor logic or the transmission factor logic. The downstream power logic may be configured to determine a power consumption amount for the second node. The power consumption amount may depend, for example, on the activity factor and the transmission factor.
Abstract:
A method and apparatus that generates a simplified, localized version (“a local stall”) of a global stall to improve the performance of a pipelined microprocessor. The local stall is generated when a data-dependency hazard is detected for a local consumer. Utilizing circuitry used in the pipelined microprocessor's data-forwarding circuitry, the local stall is generated with a relatively minor increase in circuitry. The local stall is generated much sooner than the global stall, arriving much sooner in a local pipeline. The local pipeline utilizes the local stall to override the global stall, when appropriate, and to ensure that correct data is read for a local consumer and to operate more efficiently than a standard pipeline without a local stall.
Abstract:
A note-capture application is disclosed that allows notes to be displayed on the lock screen. In one embodiment, a note-capture application can be invoked when a mobile device is in an above-lock state. Note data can be captured using the note-capture application, and the captured data can be persistently displayed on the lock screen. A user can perform a unique gesture from the lock screen to invoke the note-capture application. In another embodiment, multiple input modes can be available for note data capture. For example, voice data, text data, camera data, etc. can all be used to capture notes for display on the lock screen.
Abstract:
Systems and methods of sharing processing resources in a multi-threading environment are disclosed. An exemplary method may include allocating a lock value for a resource lock, the lock value corresponding to a state of the resource lock. A first thread may yield at least a portion of the processing resources for another thread. The resource lock may be acquired for the first thread if the lock value indicates the resource lock is available.
Abstract:
Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.
Abstract:
The method may include creating a marketing campaign, selecting a list to receive the marketing campaign, allowing the user to modify the list selected, allowing the user to add a work item to the marketing campaign and executing the marketing campaign.
Abstract:
In one embodiment of the present invention, a computer-implemented method is provided for use in a computer system including a plurality of resources. The plurality of resources include protected resources and unprotected resources. The unprotected resources include critical resources and non-critical resources. The method includes steps of: (A) receiving a request from a software program to access a specified one of the unprotected resources; (B) granting the request if the computer system is operating in a non-protected mode of operation; and (C) if the computer system is operating in a protected mode of operation, performing a step of denying the request if the computer system is not operating in a protected diagnostic mode of operation.
Abstract:
The present invention relates to a system and method for establishing an illegal system state for a table which is preferably fully associative to disable matching of prospective entries (entries to be written to the table) with entries already resident in the table. Preferably, disabling the matching of prospective and table entries forces a system for updating the fully associative table or array to employ a pointer system for writing prospective entries into the fully associative table. The illegal system may be invoked automatically upon powering up the system for updating the fully associative array or may be associated with a machine specific state effected upon issuing a specific command during program execution.