公开(公告)号：US20060031672A1

公开(公告)日：2006-02-09

申请号：US10910630

申请日：2004-08-03

申请人： Donald Soltis ,  Rohit Bhatia ,  Eric DeLano ,  Bill Greene ,  Amy Santoni

发明人： Donald Soltis ,  Rohit Bhatia ,  Eric DeLano ,  Bill Greene ,  Amy Santoni

IPC分类号： H04L9/00

CPC分类号： G06F21/6281 ,  G06F12/1027 ,  G06F12/1491 ,  G06F2221/2105

摘要： In one embodiment of the present invention, a computer-implemented method is provided for use in a computer system including a plurality of resources. The plurality of resources include protected resources and unprotected resources. The unprotected resources include critical resources and non-critical resources. The method includes steps of: (A) receiving a request from a software program to access a specified one of the unprotected resources; (B) granting the request if the computer system is operating in a non-protected mode of operation; and (C) if the computer system is operating in a protected mode of operation, performing a step of denying the request if the computer system is not operating in a protected diagnostic mode of operation.

摘要翻译： 在本发明的一个实施例中，提供了一种在包括多个资源的计算机系统中使用的计算机实现的方法。 多个资源包括受保护的资源和不受保护的资源。 未受保护的资源包括关键资源和非关键资源。 该方法包括以下步骤：（A）从软件程序接收访问指定的一个未受保护的资源的请求; （B）如果计算机系统以非保护操作模式运行，则授予请求; 以及（C）如果所述计算机系统以受保护的操作模式操作，则如果所述计算机系统未在受保护的诊断操作模式下操作，则执行拒绝所述请求的步骤。

公开(公告)号：US20060031679A1

公开(公告)日：2006-02-09

申请号：US10910652

申请日：2004-08-03

申请人： Donald Soltis ,  Rohit Bhatia ,  Eric DeLano

发明人： Donald Soltis ,  Rohit Bhatia ,  Eric DeLano

IPC分类号： H04L9/00

CPC分类号： G06F21/6281 ,  G06F2221/2105

摘要： In a computer system including a plurality of resources, techniques are disclosed for receiving a request from a software program to access a specified one of the plurality of resources, determining whether the specified one of the plurality of resources is a protected resource, and, if the specified one of the plurality of resources is a protected resource, for denying the request if the computer system is operating in a protected mode of operation, and processing the request based on access rights associated with the software program if the computer system is not operating in the protected mode of operation.

摘要翻译： 在包括多个资源的计算机系统中，公开了用于接收来自软件程序的访问多个资源中的指定的资源的请求的技术，确定所述多个资源中的指定的一个资源是否是受保护的资源，以及如果 所述多个资源中的指定的一个资源是受保护的资源，如果所述计算机系统在受保护的操作模式下操作，则拒绝所述请求，以及如果所述计算机系统未运行，则基于与所述软件程序相关联的访问权限来处理所述请求 在受保护的操作模式下。

公开(公告)号：US20050091652A1

公开(公告)日：2005-04-28

申请号：US10695267

申请日：2003-10-28

申请人： Jonathan Ross ,  Dale Morris ,  Donald Soltis ,  Rohit Bhatia ,  Eric Delano

发明人： Jonathan Ross ,  Dale Morris ,  Donald Soltis ,  Rohit Bhatia ,  Eric Delano

IPC分类号： G06F9/455

CPC分类号： G06F9/45533

摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.

摘要翻译： 虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。 这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障， 尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。

公开(公告)号：US20050138478A1

公开(公告)日：2005-06-23

申请号：US10714258

申请日：2003-11-14

申请人： Kevin Safford ,  Donald Soltis ,  Stephen Undy ,  James Gibson ,  Eric Delano

发明人： Kevin Safford ,  Donald Soltis ,  Stephen Undy ,  James Gibson ,  Eric Delano

IPC分类号： G06F11/14 ,  G06F11/00

CPC分类号： G06F11/1497 ,  G06F9/3861

摘要： Microprocessor that includes a mechanism for detecting soft errors. The processor includes an instruction fetch unit for fetching an instruction and an instruction decoder for decoding the instruction. The mechanism for detecting soft errors includes duplication hardware for duplicating the instruction and comparison hardware. The processor further includes a first execution unit for executing the instruction in a first execution cycle and the duplicated instruction in a second execution cycle. The comparison hardware compares the results of the first execution cycle and the results of the second execution cycle. The comparison hardware can include an exception unit for generating an exception (e.g., raising a fault) when the results are not the same. The processor also includes a commit unit for committing one of the results when the results are the same.

摘要翻译： 微处理器，包括检测软错误的机制。 处理器包括用于取出指令的指令获取单元和用于解码指令的指令解码器。 用于检测软错误的机制包括用于复制指令和比较硬件的复制硬件。 处理器还包括用于在第一执行周期中执行指令的第一执行单元和在第二执行周期中的复制指令。 比较硬件比较第一个执行周期的结果和第二个执行周期的结果。 当结果不相同时，比较硬件可以包括用于产生异常（例如，引起故障）的异常单元。 处理器还包括提交单元，用于在结果相同时提交其中一个结果。

公开(公告)号：US20050240810A1

公开(公告)日：2005-10-27

申请号：US10818994

申请日：2004-04-06

申请人： Kevin Safford ,  Donald Soltis ,  Eric Delano

发明人： Kevin Safford ,  Donald Soltis ,  Eric Delano

IPC分类号： G06F11/00 ,  G06F11/16 ,  G06K19/067

CPC分类号： G06F11/1641 ,  G06F11/1625 ,  G06F2201/845

摘要： A system is provided which includes a microprocessor comprising a first processing unit to generate a first output signal and a second processing unit to generate a second output signal, and comparison means, coupled to the microprocessor, to detect whether the first output signal differs from the second output signal.

摘要翻译： 提供了一种系统，其包括微处理器，该微处理器包括产生第一输出信号的第一处理单元和用于产生第二输出信号的第二处理单元，以及耦合到微处理器的比较装置，以检测第一输出信号是否与 第二输出信号。

公开(公告)号：US20050108509A1

公开(公告)日：2005-05-19

申请号：US10714093

申请日：2003-11-13

申请人： Kevin Safford ,  Donald Soltis ,  Stephen Undy ,  James Gibson ,  Eric Delano

发明人： Kevin Safford ,  Donald Soltis ,  Stephen Undy ,  James Gibson ,  Eric Delano

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F11/16 ,  G06F15/00

CPC分类号： G06F9/3885 ,  G06F9/30181 ,  G06F9/3863

摘要： A processor that includes an in-order execution architecture for executing at least two instructions per cycle (e.g., 2n instructions are processed per cycle, where n is an integer greater than or equal to one) and at least two symmetric execution units. The processor includes an instruction fetch unit for fetching n instructions (where n is an integer greater than or equal to one) and an instruction decoder for decoding the n instruction. The error detection mechanism includes duplication hardware for duplicating the n instructions into a first bundle of n instructions and a second bundle of n instructions. A first execution unit for executing the first bundle of instructions in a first execution cycle, and a second symmetric execution unit for executing the second bundle of instructions in the first execution cycle are provided. The error detection mechanism also includes comparison hardware for comparing the results of the first execution unit and the results of the second execution unit. The comparison hardware can have an exception unit for generating an exception (e.g., raising a fault) when the results are not the same. A commit unit is provided for committing one of the results when the results are the same.

摘要翻译： 一种处理器，其包括用于每个周期执行至少两个指令的按顺序执行架构（例如，每个周期处理2n个指令，其中n是大于或等于1的整数）和至少两个对称执行单元。 处理器包括用于取出n个指令（其中n是大于或等于1的整数）的指令获取单元和用于对n指令进行解码的指令解码器。 错误检测机制包括用于将n个指令复制到n个指令的第一束和第n个n个指令束中的复制硬件。 提供了用于在第一执行周期中执行第一指令集的第一执行单元和用于在第一执行周期中执行第二指令集的第二对称执行单元。 错误检测机构还包括用于比较第一执行单元的结果和第二执行单元的结果的比较硬件。 当结果不相同时，比较硬件可以具有用于产生异常（例如，引起故障）的异常单元。 当结果相同时，提交提交单元用于提交结果之一。

公开(公告)号：US20060112257A1

公开(公告)日：2006-05-25

申请号：US10987857

申请日：2004-11-12

申请人： Stephen Undy ,  Donald Soltis

发明人： Stephen Undy ,  Donald Soltis

IPC分类号： G06F15/00

CPC分类号： G01R31/318364 ,  G01R31/31707

摘要： Techniques are disclosed for generating signatures representing modifications to architected state in a microprocessor. A plurality of signals representing a plurality of architected states of a goal microprocessor may be combined to produce a goal architected state signature of the goal microprocessor. The goal microprocessor may be actual or simulated and the plurality of architected states may be actual or simulated states. A plurality of signals representing a plurality of architected states of a test microprocessor may be combined to produce a test architected state signature of the test microprocessor. The goal signature may be compared to the test signature to determine whether the test microprocessor is faulty.

摘要翻译： 公开了用于生成表示对微处理器中的架构状态的修改的签名的技术。 可以组合表示目标微处理器的多个构造状态的多个信号以产生目标微处理器的目标结构状态签名。 目标微处理器可以是实际的或模拟的，并且多个构造状态可以是实际的或模拟的状态。 可以组合表示测试微处理器的多个架构状态的多个信号以产生测试微处理器的测试架构状态签名。 可以将目标签名与测试签名进行比较，以确定测试微处理器是否有故障。

公开(公告)号：US20050268189A1

公开(公告)日：2005-12-01

申请号：US10857117

申请日：2004-05-28

申请人： Donald Soltis

发明人： Donald Soltis

IPC分类号： G01R31/28 ,  G01R31/3183

CPC分类号： G01R31/318371 ,  G01R31/318307 ,  G01R31/318314

摘要： In a device testing arrangement, a data set is selected from a set of multiple data sets, and a test kernel is selected from a set of multiple test kernels. The test kernel includes one or more instructions that utilize data. The test kernel is executed with at least some of the data from the data set, which causes one or more inputs to be provided to a device under test. A test result is obtained as one or more results generated by the device under test in response to the executing. The data set and kernel selection, execution, and result obtaining processes are repeated for one or more remaining test kernels in the set of multiple test kernels and for one or more remaining data sets in the set of multiple data sets.

摘要翻译： 在设备测试装置中，从一组多个数据集中选择数据集，并且从一组多个测试内核中选择一个测试内核。 测试内核包括一个或多个利用数据的指令。 使用数据集中的至少一些数据执行测试内核，这导致将一个或多个输入提供给被测设备。 作为响应于执行的被测设备生成的一个或多个结果，获得测试结果。 对于多个测试内核集合中的一个或多个剩余测试内核以及多组数据集中的一个或多个剩余数据集重复数据集和内核选择，执行和结果获取过程。

公开(公告)号：US20060155973A1

公开(公告)日：2006-07-13

申请号：US11034464

申请日：2005-01-13

申请人： Donald Soltis

发明人： Donald Soltis

IPC分类号： G06F9/44

CPC分类号： G06F9/462

摘要： Multithreaded hardware systems and methods are disclosed. One embodiment of a system may comprise a multithreaded processor comprising a register file having N hardware threads, where N is an integer greater than or equal to one, and an offline storage structure having M hardware threads, where M is an integer greater than or equal to one. The multithreaded processor system may further comprise a thread control that transfers register values associated with at least one of the N hardware threads to registers of at least one of the M hardware threads and transfers register values of at least of one of the M hardware threads to registers of at least one of the N hardware threads.

公开(公告)号：US20060004962A1

公开(公告)日：2006-01-05

申请号：US10883860

申请日：2004-07-02

申请人： Shawn Walker ,  Donald Soltis ,  Karl Brummel

发明人： Shawn Walker ,  Donald Soltis ,  Karl Brummel

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/0886

摘要： A cache memory system capable of adaptively accommodating various memory line sizes comprises cache memory and cache logic. The cache memory has sets of ways. The cache logic is configured to request a memory line in response to a cache miss, and the memory line represents a portion of a way line. The cache logic is configured to select one of the ways based on which portion of the way line is represented by the memory line. The cache logic is further configured to store the memory line in the selected way.