公开(公告)号：US20130326582A1

公开(公告)日：2013-12-05

申请号：US13489165

申请日：2012-06-05

申请人： Michael J. Kruzeniski ,  Joseph B. Tobens ,  Jon Bell ,  William Scott Stauber ,  Rohit Bhatia ,  Ram Pattabhi Papatla ,  Daniel Escapa

发明人： Michael J. Kruzeniski ,  Joseph B. Tobens ,  Jon Bell ,  William Scott Stauber ,  Rohit Bhatia ,  Ram Pattabhi Papatla ,  Daniel Escapa

IPC分类号： G06F21/00

CPC分类号： G06F3/04883 ,  G06F21/604 ,  G06F21/6209 ,  G06F2221/2149

摘要： A note-capture application is disclosed that allows notes to be displayed on the lock screen. In one embodiment, a note-capture application can be invoked when a mobile device is in an above-lock state. Note data can be captured using the note-capture application, and the captured data can be persistently displayed on the lock screen. A user can perform a unique gesture from the lock screen to invoke the note-capture application. In another embodiment, multiple input modes can be available for note data capture. For example, voice data, text data, camera data, etc. can all be used to capture notes for display on the lock screen.

摘要翻译： 公开了一种允许在锁屏上显示笔记的记录捕获应用程序。 在一个实施例中，当移动设备处于上述锁定状态时，可以调用音符捕获应用。 记录数据可以使用记录捕获应用程序进行捕获，捕获的数据可以持续显示在锁定屏幕上。 用户可以从锁定屏幕执行唯一的手势来调用音符捕获应用程序。 在另一个实施例中，多个输入模式可用于笔记数据捕获。 例如，语音数据，文本数据，相机数据等都可以用于捕获在锁屏幕上显示的笔记。

公开(公告)号：US09009630B2

公开(公告)日：2015-04-14

申请号：US13489165

申请日：2012-06-05

申请人： Michael J. Kruzeniski ,  Joseph B. Tobens ,  Jon Bell ,  William Scott Stauber ,  Rohit Bhatia ,  Ram Pattabhi Papatla ,  Daniel Escapa

发明人： Michael J. Kruzeniski ,  Joseph B. Tobens ,  Jon Bell ,  William Scott Stauber ,  Rohit Bhatia ,  Ram Pattabhi Papatla ,  Daniel Escapa

IPC分类号： G06F3/048 ,  G06F3/0488 ,  G06F21/60 ,  G06F3/14

CPC分类号： G06F3/04883 ,  G06F21/604 ,  G06F21/6209 ,  G06F2221/2149

摘要： A note-capture application is disclosed that allows notes to be displayed on the lock screen. In one embodiment, a note-capture application can be invoked when a mobile device is in an above-lock state. Note data can be captured using the note-capture application, and the captured data can be persistently displayed on the lock screen. A user can perform a unique gesture from the lock screen to invoke the note-capture application. In another embodiment, multiple input modes can be available for note data capture. For example, voice data, text data, camera data, etc. can all be used to capture notes for display on the lock screen.

摘要翻译： 公开了一种允许在锁屏上显示笔记的记录捕获应用程序。 在一个实施例中，当移动设备处于上述锁定状态时，可以调用音符捕获应用。 记录数据可以使用记录捕获应用程序进行捕获，捕获的数据可以持续显示在锁定屏幕上。 用户可以从锁定屏幕执行唯一的手势来调用音符捕获应用程序。 在另一个实施例中，多个输入模式可用于笔记数据捕获。 例如，语音数据，文本数据，相机数据等都可以用于捕获在锁屏幕上显示的笔记。

公开(公告)号：US09348766B2

公开(公告)日：2016-05-24

申请号：US13994690

申请日：2011-12-21

申请人： Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

发明人： Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

IPC分类号： G06F13/00 ,  G06F12/12 ,  G06F3/06 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F12/122 ,  G06F3/0604 ,  G06F12/00 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/124 ,  G06F12/125

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N−1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a “multiple of 5” number of cache ways, and variations of the “multiple of 3” number of cache ways.

摘要翻译： 根据本文公开的实施例，提供了用于实现用于“3”倍的方式缓存的平衡P-LRU树的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。 在这样的实施例中，多个方式包括量是三的倍数而不是二的幂，并且其中多个方式被组织成多对。 在这种实施例中，装置还包括用于多个对中的每一对的单个比特，其中每个单个比特将用作表示相关联的一对路由的中间级别决策节点，以及具有正好两个单独比特的根级别决策节点 指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。 在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。 还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

公开(公告)号：US09069690B2

公开(公告)日：2015-06-30

申请号：US13613777

申请日：2012-09-13

申请人： Gur Hildesheim ,  Chang Kian Tan ,  Robert S. Chappell ,  Rohit Bhatia

发明人： Gur Hildesheim ,  Chang Kian Tan ,  Robert S. Chappell ,  Rohit Bhatia

IPC分类号： G06F12/10

CPC分类号： G06F12/10 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/651 ,  G06F2212/655 ,  G06F2212/681 ,  G06F2212/684

摘要： In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，页面未命中处理程序包括寻呼高速缓存和第一步行器，以接收第一线性地址部分并且从寻呼结构获得物理地址的对应部分，与第一步行者并行操作的第二步行者，以及 用于防止第一步行器响应于匹配由第二步行者访问的并行寻呼结构的对应线性地址部分的第一线性地址部分而将所获得的物理地址部分存储在寻呼高速缓存器中的逻辑。 描述和要求保护其他实施例。

公开(公告)号：US08479029B2

公开(公告)日：2013-07-02

申请号：US13167970

申请日：2011-06-24

申请人： Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

发明人： Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3234 ,  G06F1/3203

摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

公开(公告)号：US20110252255A1

公开(公告)日：2011-10-13

申请号：US13167970

申请日：2011-06-24

申请人： Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

发明人： Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

IPC分类号： G06F1/32

CPC分类号： G06F1/3234 ,  G06F1/3203

摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

摘要翻译： 公开了减少处理器的步进负载的方法和装置。 方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集 号码来控制执行期间的电量。 一些实施例还可以创建人为活动以为处理器提供最小功率层。 装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑 的执行期间要处理的指令。

公开(公告)号：US07992017B2

公开(公告)日：2011-08-02

申请号：US11900316

申请日：2007-09-11

申请人： Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

发明人： Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

IPC分类号： G06F1/32 ,  G06F11/30

CPC分类号： G06F1/3234 ,  G06F1/3203

摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

摘要翻译： 公开了减少处理器的步进负载的方法和装置。 方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并且将执行限制到指令的子集 号码来控制执行期间的电量。 一些实施例还可以创建人为活动以为处理器提供最小功率层。 装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑 的执行期间要处理的指令。

公开(公告)号：US20140181484A1

公开(公告)日：2014-06-26

申请号：US13725934

申请日：2012-12-21

申请人： James Callister ,  Don Soltis ,  Rohit Bhatia ,  Ramkumar Srinivasan ,  Steven Bostian ,  Richard M. Blumberg

发明人： James Callister ,  Don Soltis ,  Rohit Bhatia ,  Ramkumar Srinivasan ,  Steven Bostian ,  Richard M. Blumberg

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/4881

摘要： According to one embodiment, a processor includes an execution pipeline for executing a plurality of threads, including a first thread and a second thread. The processor further includes a multi-thread controller (MTC) coupled to the execution pipeline to determine whether to switch threads between the first and second thread based on a thread switch policy that is selected from a list of thread switch policies based on unfairness levels of the first and second thread, and in response to determining to switch threads, to switch from executing the first thread to executing the second thread.

摘要翻译： 根据一个实施例，处理器包括用于执行包括第一线程和第二线程的多个线程的执行流水线。 处理器还包括耦合到执行流水线的多线程控制器（MTC），以基于从线程切换策略列表中选择的线程切换策略来确定是否在第一和第二线程之间切换线程，所述线程切换策略基于线程切换策略的列表， 第一线程和第二线程，并且响应于确定切换线程，从执行第一线程切换到执行第二线程。

公开(公告)号：US20130275787A1

公开(公告)日：2013-10-17

申请号：US13913864

申请日：2013-06-10

申请人： Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

发明人： Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

IPC分类号： G06F1/32

CPC分类号： G06F1/3234 ,  G06F1/3203

摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

摘要翻译： 公开了减少处理器的步进负载的方法和装置。 方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集 号码来控制执行期间的电量。 一些实施例还可以创建人为活动以为处理器提供最小功率层。 装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑 的执行期间要处理的指令。

公开(公告)号：US20120023036A1

公开(公告)日：2012-01-26

申请号：US13190655

申请日：2011-07-26

申请人： MICHAEL SCHMANSKE ,  Maneesh Deshpande ,  Rohit Bhatia ,  Yidong Ding ,  Pankaj Khandelwal

发明人： MICHAEL SCHMANSKE ,  Maneesh Deshpande ,  Rohit Bhatia ,  Yidong Ding ,  Pankaj Khandelwal

IPC分类号： G06Q40/00

CPC分类号： G06Q40/04 ,  G06Q40/06

摘要： An exemplary aspect comprises receiving data related to an underlying asset; calculating values corresponding to near-term implied volatility and realized volatility for the underlying asset; and transmitting data sufficient to describe an index based on a difference between the values corresponding to the near-term implied volatility and the realized volatility for the underlying asset. Another exemplary aspect comprises receiving electronic data related to an underlying asset; calculating data sufficient to describe a plurality of call options and a plurality of put options related to the underlying asset and written on a first settlement date; crediting an account with proceeds from selling the call and put options; and debiting the account to settle one or more of the options that are in-the-money on a second settlement date. Other aspects are apparent from the description and claims.

摘要翻译： 示例性方面包括接收与标的资产相关的数据; 计算相应资产的近期隐含波动率和实现波动率的值; 并且基于与短期隐含波动率相对应的值与标的资产的实现波动率之间的差异来传送足以描述指数的数据。 另一示例性方面包括接收与标的资产相关的电子数据; 计算足以描述多个看涨期权的数据和与相关资产相关并在第一结算日期写入的多个看跌期权; 记入销售电话和放置期权的收益; 并借记帐户以在第二个结算日期结算一个或多个在货币中的期权。 从描述和权利要求中，其它方面是显而易见的。