公开(公告)号：US20110063904A1

公开(公告)日：2011-03-17

申请号：US12879157

申请日：2010-09-10

Applicant: Sang-Hoan CHANG ,  Seong-Moo HEO ,  Kwang-Suk YU ,  Yeong-Taek LEE ,  Woo-Yeong CHO

Inventor： Sang-Hoan CHANG ,  Seong-Moo HEO ,  Kwang-Suk YU ,  Yeong-Taek LEE ,  Woo-Yeong CHO

IPC: G11C11/21 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0057 ,  G11C2013/0092 ,  G11C2213/56

Abstract: A method of programming a phase change memory device is disclosed. Write data is programmed in a plurality of phase change memory cells by applying write pulses to each of the plurality of phase change memory cells. Whether each of the phase change memory cells is programmed is verified by applying at least one verification pulse to each of the phase-change memory cells. A number of applications for the at least one verification pulse and the intervals between respective applications of the at least one verification pulse are varied in accordance with a verification result for each of the phase-change memory cells.

Abstract translation: 公开了一种编程相变存储器件的方法。 通过向多个相变存储单元中的每一个施加写脉冲，将写数据编程在多个相变存储单元中。 通过对每个相变存储单元施加至少一个验证脉冲来验证每个相变存储器单元是否被编程。 至少一个验证脉冲的应用程序和至少一个验证脉冲的相应应用之间的间隔的数量根据每个相变存储单元的验证结果而变化。

公开(公告)号：US20090168534A1

公开(公告)日：2009-07-02

申请号：US12343636

申请日：2008-12-24

Applicant: Ki-Tae PARK ,  Yeong-Taek LEE

Inventor： Ki-Tae PARK ,  Yeong-Taek LEE

IPC: G11C16/06 ,  G11C5/02 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C16/0483 ,  G11C5/02 ,  G11C5/025 ,  G11C8/14 ,  G11C8/18 ,  H01L21/8221 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551

Abstract: Disclosed is a 3D memory device including a first plane having a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats sharing a bit line, and a second plane having a second mat formed on the first layer and a fourth mat formed on the second layer. The second and fourth mats share a bit line. Each one of the first through fourth mats includes a plurality of blocks and a block associated with the first plane is simultaneously accessed with a block of the second plane.

Abstract translation: 公开了一种3D存储器件，其包括具有形成在第一层上的第一垫的第一平面和形成在第一层上的第二层上的第三垫，第一和第三垫共享位线，第二平面具有 形成在第一层上的第二垫和形成在第二层上的第四垫。 第二和第四垫共享一点。 第一至第四垫中的每一个包括多个块，并且与第一平面相关联的块与第二平面的块同时访问。

公开(公告)号：US20090168533A1

公开(公告)日：2009-07-02

申请号：US12343632

申请日：2008-12-24

Applicant: Ki-Tae PARK ,  Yeong-Taek LEE

Inventor： Ki-Tae PARK ,  Yeong-Taek LEE

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C16/0483 ,  G11C5/02 ,  G11C8/14 ,  G11C16/10 ,  H01L21/8221 ,  H01L27/115 ,  H01L27/11578

Abstract: A programming method and a three-dimensional memory device are disclosed. The three-dimensional memory device includes a stacked plurality of layers, each layer having a memory array, and each memory array having a string of memory cells. The programming method includes, for each unselected string associated with an unselected layer in the plurality of layers, charging the channel of memory cells associated with unselected string with a shut-off voltage, and thereafter programming a selected string associated with a selected layer in the plurality of layers.

Abstract translation: 公开了一种编程方法和三维存储器件。 三维存储器件包括堆叠的多个层，每个层具有存储器阵列，并且每个存储器阵列具有一串存储器单元。 编程方法包括对于与多个层中的未选择层相关联的每个未选择的字符串，对具有关闭电压的与未选择的字符串相关联的存储器单元的通道进行充电，然后对与所选择的层相关联的所选字符串进行编程 多层。

公开(公告)号：US20080205163A1

公开(公告)日：2008-08-28

申请号：US12035732

申请日：2008-02-22

Applicant: Ki-Tae PARK ,  Ki-Nam KIM ,  Yeong-Taek LEE

Inventor： Ki-Tae PARK ,  Ki-Nam KIM ,  Yeong-Taek LEE

IPC: G11C16/06

CPC classification number: G11C11/5621 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454

Abstract: Provided are a nonvolatile memory device and a driving method thereof. In the method of driving a nonvolatile memory device, a structural shape and position of a memory cell to be driven is determined, and then the memory cell is driven with an optimized operating condition according to a distribution of the memory cell using a determination result.

Abstract translation: 提供一种非易失性存储装置及其驱动方法。 在驱动非易失性存储器件的方法中，确定要驱动的存储单元的结构形状和位置，然后使用确定结果根据存储单元的分布以优化的操作条件驱动存储单元。

公开(公告)号：US20080144370A1

公开(公告)日：2008-06-19

申请号：US11940526

申请日：2007-11-15

Applicant: Ki-Tae PARK ,  Yeong-Taek LEE ,  Ki-Nam KIM ,  Doo-Gon KIM

Inventor： Ki-Tae PARK ,  Yeong-Taek LEE ,  Ki-Nam KIM ,  Doo-Gon KIM

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14

Abstract: A non-volatile memory device has multi-level cells (MLCs), which are programmed such that one page is written in the MLCs having previous states corresponding to at least one previous page. The non-volatile memory device includes a memory cell array, a row selection circuit and a page buffer block. The memory cell array includes the MLCs commonly coupled to a selected word line and respectively coupled to bitlines. The row selection circuit applies sequentially-decreasing read voltages to the selected wordline to read the previous states of the MLCs, and sequentially-decreasing verification voltages to the selected wordline to program states of the MLCs sequentially from a state having a highest threshold voltage to a state having a lowest threshold voltage. The page buffer block loads data corresponding to the one page, and controls a bitline voltage based on each previous state and each bit of the loaded data.

Abstract translation: 非易失性存储器件具有多级单元（MLC），其被编程为使得一页被写入具有对应于至少一个先前页的先前状态的MLC。 非易失性存储器件包括存储单元阵列，行选择电路和页缓冲块。 存储单元阵列包括通常耦合到所选字线并分别耦合到位线的MLC。 行选择电路对所选择的字线应用顺序递减的读取电压以读取MLC的先前状态，并且顺序地减小对所选字线的验证电压，以从具有最高阈值电压的状态顺序地编程MLC的状态， 状态具有最低阈值电压。 页面缓冲区块加载对应于一页的数据，并且基于每个先前状态和加载的数据的每个位来控制位线电压。