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    NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD WITH IMPROVED PASS VOLTAGE WINDOW
    1.
    发明申请
    NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD WITH IMPROVED PASS VOLTAGE WINDOW 有权
    非易失性存储器件和具有改进的电压窗口的程序方法

    公开(公告)号：US20100067305A1

    公开(公告)日：2010-03-18

    申请号：US12509612

    申请日：2009-07-27

    Applicant: Ki-Tae PARK ,  Yeong-Taek LEE ,  Soon-Wook HWANG ,  Young-Wook JEONG

    Inventor： Ki-Tae PARK ,  Yeong-Taek LEE ,  Soon-Wook HWANG ,  Young-Wook JEONG

    IPC: G11C16/04 ,  G11C5/14

    CPC classification number: G11C16/12 ,  G11C16/0483

    Abstract: A flash memory and programming method are disclosed. The flash memory includes a memory cell array having memory cells arranged in a plurality of word lines including a selected word line and a plurality of non-selected word lines and a plurality of bit lines, a high voltage generator generating a program voltage applied to the selected word line, and a pass voltage applied to at least one of the non-selected word lines adjacent to the selected word line, and control logic controlling the generation of the program voltage, such that the program voltage is incrementally increased during a program operation, and generation of the pass voltage, such that the program voltage is incrementally increased.

    Abstract translation: 公开了闪存和编程方法。 闪速存储器包括存储单元阵列，该存储单元阵列具有布置在包括所选择的字线和多个未选择的字线和多个位线的多个字线中的存储器单元，高电压发生器产生施加到该字线的编程电压 所选择的字线和施加到与所选字线相邻的未选择的字线中的至少一个的通过电压，以及控制逻辑，以控制编程电压的产生，使得编程电压在编程操作期间递增地增加 ，并产生通过电压，使得编程电压递增地增加。

    NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING
    2.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING 有权
    非易失性存储器件和操作方法

    公开(公告)号：US20080316818A1

    公开(公告)日：2008-12-25

    申请号：US12141737

    申请日：2008-06-18

    Applicant: Ki-Tae PARK ,  Doo-Gon KIM ,  Yeong-Taek LEE

    Inventor： Ki-Tae PARK ,  Doo-Gon KIM ,  Yeong-Taek LEE

    IPC: G11C16/06

    CPC classification number: G11C16/3418

    Abstract: A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage.

    Abstract translation: 一种非易失性存储器件和操作方法，包括向多个存储器单元内的所选存储单元的栅极提供验证电压，并且在程序验证期间向存储器单元内的未选择存储单元的栅极提供第一通过电压 操作; 以及向所选择的存储单元的栅极提供读取电压，并且在读取操作期间向未选择的存储单元的栅极提供第二通过电压。 第二通过电压大于第一通过电压。

    THREE-DIMENSIONAL MEMORY DEVICE
    5.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE 审中-公开
    三维存储器件

    公开(公告)号：US20090168482A1

    公开(公告)日：2009-07-02

    申请号：US12343630

    申请日：2008-12-24

    Applicant: Ki-Tae PARK ,  Yeong-Taek LEE ,  Doo-Gon KIM

    Inventor： Ki-Tae PARK ,  Yeong-Taek LEE ,  Doo-Gon KIM

    IPC: G11C17/08 ,  G11C5/02

    CPC classification number: G11C16/0483 ,  G11C5/02 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    Abstract: A three-dimensional memory device includes a base layer having a memory array and peripheral circuits formed on a bulk silicon substrate, and N circuit layers each having a memory array formed on a silicon-on-insulator (SOI) substrate. The N circuit layers are vertically stacked one on top of the other on the base layer and the uppermost Nth circuit layer additionally includes passive elements

    Abstract translation: 三维存储器件包括具有存储器阵列的基底层和形成在体硅衬底上的外围电路，以及每个具有形成在绝缘体上硅（SOI））衬底上的存储器阵列的N个电路层。 N个电路层在基极层上垂直堆叠在一起，而最上面的第N个电路层另外包括无源元件

    METHOD OF ERASING IN NON-VOLATILE MEMORY DEVICE
    6.
    发明申请
    METHOD OF ERASING IN NON-VOLATILE MEMORY DEVICE 有权
    非易失性存储器件中的擦除方法

    公开(公告)号：US20080304326A1

    公开(公告)日：2008-12-11

    申请号：US12136968

    申请日：2008-06-11

    Applicant: Doo-Gon KIM ,  Ki-Tae PARK ,  Yeong-Taek LEE

    Inventor： Doo-Gon KIM ,  Ki-Tae PARK ,  Yeong-Taek LEE

    IPC: G11C16/06

    CPC classification number: G11C16/14

    Abstract: An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage.

    Abstract translation: 一种在非易失性存储器件中进行后编程的擦除方法。 该方法包括后编程虚拟存储器单元; 验证所述伪存储单元的阈值电压是否大于或等于第一电压; 后编程正常记忆单元; 以及验证所述正常存储单元的阈值电压是否大于或等于第二电压。 第一电压与第二电压不同。

    THREE-DIMENSIONAL MEMORY DEVICE WITH MULTI-PLANE ARCHITECTURE
    8.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH MULTI-PLANE ARCHITECTURE 有权
    具有多平面架构的三维存储器件

    公开(公告)号：US20090168534A1

    公开(公告)日：2009-07-02

    申请号：US12343636

    申请日：2008-12-24

    Applicant: Ki-Tae PARK ,  Yeong-Taek LEE

    Inventor： Ki-Tae PARK ,  Yeong-Taek LEE

    IPC: G11C16/06 ,  G11C5/02 ,  G11C7/00 ,  G11C8/00

    CPC classification number: G11C16/0483 ,  G11C5/02 ,  G11C5/025 ,  G11C8/14 ,  G11C8/18 ,  H01L21/8221 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551

    Abstract: Disclosed is a 3D memory device including a first plane having a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats sharing a bit line, and a second plane having a second mat formed on the first layer and a fourth mat formed on the second layer. The second and fourth mats share a bit line. Each one of the first through fourth mats includes a plurality of blocks and a block associated with the first plane is simultaneously accessed with a block of the second plane.

    Abstract translation: 公开了一种3D存储器件，其包括具有形成在第一层上的第一垫的第一平面和形成在第一层上的第二层上的第三垫，第一和第三垫共享位线，第二平面具有 形成在第一层上的第二垫和形成在第二层上的第四垫。 第二和第四垫共享一点。 第一至第四垫中的每一个包括多个块，并且与第一平面相关联的块与第二平面的块同时访问。

    THREE-DIMENSIONAL MEMORY DEVICE AND PROGRAMMING METHOD
    9.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE AND PROGRAMMING METHOD 有权
    三维存储器件和编程方法

    公开(公告)号：US20090168533A1

    公开(公告)日：2009-07-02

    申请号：US12343632

    申请日：2008-12-24

    Applicant: Ki-Tae PARK ,  Yeong-Taek LEE

    Inventor： Ki-Tae PARK ,  Yeong-Taek LEE

    IPC: G11C16/06 ,  G11C7/00

    CPC classification number: G11C16/0483 ,  G11C5/02 ,  G11C8/14 ,  G11C16/10 ,  H01L21/8221 ,  H01L27/115 ,  H01L27/11578

    Abstract: A programming method and a three-dimensional memory device are disclosed. The three-dimensional memory device includes a stacked plurality of layers, each layer having a memory array, and each memory array having a string of memory cells. The programming method includes, for each unselected string associated with an unselected layer in the plurality of layers, charging the channel of memory cells associated with unselected string with a shut-off voltage, and thereafter programming a selected string associated with a selected layer in the plurality of layers.

    Abstract translation: 公开了一种编程方法和三维存储器件。 三维存储器件包括堆叠的多个层，每个层具有存储器阵列，并且每个存储器阵列具有一串存储器单元。 编程方法包括对于与多个层中的未选择层相关联的每个未选择的字符串，对具有关闭电压的与未选择的字符串相关联的存储器单元的通道进行充电，然后对与所选择的层相关联的所选字符串进行编程 多层。

    NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF
    10.
    发明申请
    NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF 有权
    非易失性存储器件及其驱动方法

    公开(公告)号：US20080205163A1

    公开(公告)日：2008-08-28

    申请号：US12035732

    申请日：2008-02-22

    Applicant: Ki-Tae PARK ,  Ki-Nam KIM ,  Yeong-Taek LEE

    Inventor： Ki-Tae PARK ,  Ki-Nam KIM ,  Yeong-Taek LEE

    IPC: G11C16/06

    CPC classification number: G11C11/5621 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454

    Abstract: Provided are a nonvolatile memory device and a driving method thereof. In the method of driving a nonvolatile memory device, a structural shape and position of a memory cell to be driven is determined, and then the memory cell is driven with an optimized operating condition according to a distribution of the memory cell using a determination result.

    Abstract translation: 提供一种非易失性存储装置及其驱动方法。 在驱动非易失性存储器件的方法中，确定要驱动的存储单元的结构形状和位置，然后使用确定结果根据存储单元的分布以优化的操作条件驱动存储单元。

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