公开(公告)号：US06708269B1

公开(公告)日：2004-03-16

申请号：US09475098

申请日：1999-12-30

申请人： Keshavan K. Tiruvallur ,  Douglas M. Carmean ,  Robert J. Greiner ,  Muntaquim Chowdhury ,  Madhavan Parthasarathy

发明人： Keshavan K. Tiruvallur ,  Douglas M. Carmean ,  Robert J. Greiner ,  Muntaquim Chowdhury ,  Madhavan Parthasarathy

IPC分类号： G06F9312

CPC分类号： G06F9/3824 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3842 ,  G06F9/3851

摘要： In a multi-threaded system, such as in a multi-processor system, different types of fences are provided to force completion of programmatically earlier instructions in a program. The types of fences can be thread-specific, and different types of fences are used based on different kinds of conditions, instructions, operations, or memory types. When a fence is executed, senior stores, request buffers, bus queues, or any combination of these stages in an execution pipeline can be drained. Fetches at a front end of the pipeline can also be killed to ensure that the bus queue can be drained.

摘要翻译： 在多线程系统中，例如在多处理器系统中，提供了不同类型的围栏，以强制程序化程序中早期指令的完成。 栅栏的类型可以是线程特定的，并且基于不同种类的条件，指令，操作或存储器类型使用不同类型的栅栏。 执行栅栏时，执行管道中的高级存储，请求缓冲区，总线队列或这些阶段的任意组合可能会被排除。 管道前端的汲取也可能被杀死，以确保总线队列可以排空。

公开(公告)号：US06629271B1

公开(公告)日：2003-09-30

申请号：US09472839

申请日：1999-12-28

申请人： Yung-Hsiang Lee ,  Douglas M. Carmean ,  Rohit A. Vidwans

发明人： Yung-Hsiang Lee ,  Douglas M. Carmean ,  Rohit A. Vidwans

IPC分类号： H02H305

CPC分类号： G06F9/3855 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

摘要： A computer processor includes a replay system to replay instructions which have not executed properly and a first event pipeline coupled to the replay system to process instructions including any replayed instructions. A second event pipeline is provided to perform additional processing on an instruction. The second event pipeline has an ability to detect one or more faults occurring therein. The processor also includes a synchronization circuit coupled between the first event pipeline and the second event pipeline to synchronize faults occurring in the second event pipeline to matching instruction entries in the first event pipeline.

摘要翻译： 计算机处理器包括重播系统以重播没有正确执行的指令以及耦合到重放系统的第一事件流水线来处理包括任何重播指令的指令。 提供第二个事件流水线来对指令执行附加处理。 第二事件管道具有检测其中发生的一个或多个故障的能力。 处理器还包括耦合在第一事件流水线和第二事件流水线之间的同步电路，用于将第二事件流水线中发生的故障与第一事件流水线中的匹配指令条目进行同步。

公开(公告)号：US06484254B1

公开(公告)日：2002-11-19

申请号：US09475922

申请日：1999-12-30

申请人： Muntaquim F. Chowdhury ,  Douglas M. Carmean

发明人： Muntaquim F. Chowdhury ,  Douglas M. Carmean

IPC分类号： G06F938

CPC分类号： G06F9/3851 ,  G06F9/3834

摘要： According to one aspect of the invention, a method is provided in which store addresses of store instructions dispatched during a last predetermined number of cycles are maintained in a first data structure of a first processor. It is determined whether a load address of a first load instruction matches one of the store addresses in the first data structure. The first load instruction is replayed if the load address of the first load instruction matches one of the store addresses in the first data structure.

摘要翻译： 根据本发明的一个方面，提供了一种方法，其中在最后一个预定次数的周期期间调度的存储指令的存储地址保持在第一处理器的第一数据结构中。 确定第一加载指令的加载地址是否匹配第一数据结构中的一个存储地址。 如果第一个加载指令的加载地址与第一个数据结构中的一个存储地址匹配，则重播第一个加载指令。

公开(公告)号：US20140149651A1

公开(公告)日：2014-05-29

申请号：US13685991

申请日：2012-11-27

申请人： Andrew T. Forsyth ,  Ramacharan Sundararaman ,  Eric Sprangle ,  John C. Mejia ,  Douglas M. Carmean ,  Mark C. Davis ,  Edward T. Grochowski ,  Robert D. Cavin

发明人： Andrew T. Forsyth ,  Ramacharan Sundararaman ,  Eric Sprangle ,  John C. Mejia ,  Douglas M. Carmean ,  Mark C. Davis ,  Edward T. Grochowski ,  Robert D. Cavin

IPC分类号： G06F12/08

CPC分类号： G06F12/126 ,  G06F12/123 ,  Y02D10/13

摘要： In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括解码逻辑，用于接收和解码第一存储器访问指令以将数据存储在具有第一级的替换状态指示符的高速缓冲存储器中，并将解码的第一存储器访问指令发送到控制逻辑。 反过来，控制逻辑是以第一组高速缓冲存储器的第一种方式存储数据，并且响应于解码的第一存储器访问指令将第一级的替换状态指示符存储在第一方式的元数据字段中 。 描述和要求保护其他实施例。

公开(公告)号：US08667250B2

公开(公告)日：2014-03-04

申请号：US11964631

申请日：2007-12-26

申请人： Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

发明人： Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

IPC分类号： G06F9/312

CPC分类号： G06F9/30025 ,  G06F9/30036 ,  G06F9/30043

摘要： A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

摘要翻译： 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。

公开(公告)号：US20130232318A1

公开(公告)日：2013-09-05

申请号：US13844111

申请日：2013-03-15

申请人： Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

发明人： Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

IPC分类号： G06F9/30

CPC分类号： G06F9/30025 ,  G06F9/30036 ,  G06F9/30043

摘要： A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

公开(公告)号：US07743233B2

公开(公告)日：2010-06-22

申请号：US11100032

申请日：2005-04-05

申请人： Hong Wang ,  Gautham N. Chinya ,  Richard A. Hankins ,  Shivnandan D. Kaushik ,  Bryant Bigbee ,  John Shen ,  Per Hammarlund ,  Xiang Zou ,  Jason W. Brandt ,  Prashant Sethi ,  Douglas M. Carmean ,  Baiju V. Patel ,  Scott Dion Rodgers ,  Ryan N. Rakvic ,  John L. Reid ,  David K. Poulsen ,  Sanjiv M. Shah ,  James Paul Held ,  James Charles Abel

发明人： Hong Wang ,  Gautham N. Chinya ,  Richard A. Hankins ,  Shivnandan D. Kaushik ,  Bryant Bigbee ,  John Shen ,  Per Hammarlund ,  Xiang Zou ,  Jason W. Brandt ,  Prashant Sethi ,  Douglas M. Carmean ,  Baiju V. Patel ,  Scott Dion Rodgers ,  Ryan N. Rakvic ,  John L. Reid ,  David K. Poulsen ,  Sanjiv M. Shah ,  James Paul Held ,  James Charles Abel

IPC分类号： G06F9/00

CPC分类号： G06F9/485 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/461 ,  G06F9/4881

摘要： Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

摘要翻译： 公开了用于管理和转换逻辑定序器地址与多序列器多线程系统中的物理或逻辑顺控程序之间的映射的系统，方法和机制的实施例。 映射管理器可以管理逻辑顺控程序地址或页面到系统的实际定序器或帧的分配和映射。 与映射管理器相关联的配给逻辑可以在执行这样的映射时考虑定序器属性。当重新映射实际的定序器时，与映射管理器相关联的重定位逻辑可以管理向/从备份存储器的上下文信息的溢出和填充。 排序器可以单独分配，或者可以被分配为分区块的一部分。 映射管理器还可以包括每当在用户程序中使用逻辑定序器地址时为映射的定序器提供标识符的翻译逻辑。 还描述和要求保护其他实施例。

公开(公告)号：US06880069B1

公开(公告)日：2005-04-12

申请号：US09608567

申请日：2000-06-30

申请人： Douglas M. Carmean ,  David J. Sager ,  Thomas F. Toll ,  Karol F. Menezes

发明人： Douglas M. Carmean ,  David J. Sager ,  Thomas F. Toll ,  Karol F. Menezes

IPC分类号： G06F9/38

CPC分类号： G06F9/3861

摘要： Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously.

公开(公告)号：US06877086B1

公开(公告)日：2005-04-05

申请号：US09705678

申请日：2000-11-02

申请人： Darrell D. Boggs ,  Douglas M. Carmean ,  Per H. Hammarlund ,  Francis X. McKeen ,  David J. Sager ,  Ronak Singhal

发明人： Darrell D. Boggs ,  Douglas M. Carmean ,  Per H. Hammarlund ,  Francis X. McKeen ,  David J. Sager ,  Ronak Singhal

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3861

摘要： Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

摘要翻译： 使用重放队列在处理器中重新安排多个微操作。 处理器包括用于接收多个指令的重放队列和执行多个指令的执行单元。 调度器耦合在重播队列和执行单元之间。 调度器推测性地安排执行指令并将每个指令分派到执行单元。 检查器耦合到执行单元以确定每个指令是否已成功执行。 检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

公开(公告)号：US5669003A

公开(公告)日：1997-09-16

申请号：US363744

申请日：1994-12-23

申请人： Douglas M. Carmean ,  John Crawford

发明人： Douglas M. Carmean ,  John Crawford

IPC分类号： G06F1/32 ,  G06F12/08

CPC分类号： G06F1/3215 ,  G06F1/3275 ,  G06F12/0831 ,  G06F2212/1028 ,  Y02B60/1225 ,  Y02B60/1228

摘要： A method for maintaining cache coherency while minimizing the power consumption. The method includes operating a first processor in a reduced power mode. While the first processor is operating in a reduced power mode, certain portions of the internal logic in the first processor remain clocked so that the first processor continues to monitor transactions on the system bus. The second processor runs a transaction on the system bus to request data. In the event that the first processor determines that the transaction by the second processor is requesting cache data that is stored in the first processor in a modified state, the first processor signals the second processor. After the current bus cycle is completed, the first processor writes back the modified cache line on the system bus and second processor re-runs the transaction on the system bus.

摘要翻译： 一种在最小化功耗的同时保持高速缓存一致性的方法。 该方法包括以降低功率模式操作第一处理器。 当第一处理器以降低功率模式运行时，第一处理器中的内部逻辑的某些部分保持时钟，使得第一处理器继续监视系统总线上的事务。 第二个处理器在系统总线上运行事务以请求数据。 在第一处理器确定第二处理器的事务请求处于修改状态的第一处理器中存储的高速缓存数据的情况下，第一处理器向第二处理器发信号。 当前总线周期完成后，第一个处理器将修改后的高速缓存行写入系统总线，第二个处理器在系统总线上重新运行事务。