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公开(公告)号：US20140149651A1
公开(公告)日：2014-05-29
申请号：US13685991
申请日：2012-11-27
申请人： Andrew T. Forsyth , Ramacharan Sundararaman , Eric Sprangle , John C. Mejia , Douglas M. Carmean , Mark C. Davis , Edward T. Grochowski , Robert D. Cavin
发明人： Andrew T. Forsyth , Ramacharan Sundararaman , Eric Sprangle , John C. Mejia , Douglas M. Carmean , Mark C. Davis , Edward T. Grochowski , Robert D. Cavin
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/123 , Y02D10/13
摘要： In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括解码逻辑，用于接收和解码第一存储器访问指令以将数据存储在具有第一级的替换状态指示符的高速缓冲存储器中，并将解码的第一存储器访问指令发送到控制逻辑。 反过来，控制逻辑是以第一组高速缓冲存储器的第一种方式存储数据，并且响应于解码的第一存储器访问指令将第一级的替换状态指示符存储在第一方式的元数据字段中 。 描述和要求保护其他实施例。
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2.发明授权公开(公告)号：US08533436B2
公开(公告)日：2013-09-10
申请号：US12492652
申请日：2009-06-26
申请人： Joshua B. Fryman , Edward T. Grochowski , Toni Juan , Andrew Thomas Forsyth , John Mejia , Ramacharan Sundararaman , Eric Sprangle , Roger Espasa , Ravi Rajwar
发明人： Joshua B. Fryman , Edward T. Grochowski , Toni Juan , Andrew Thomas Forsyth , John Mejia , Ramacharan Sundararaman , Eric Sprangle , Roger Espasa , Ravi Rajwar
CPC分类号： G06F9/30185 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3861 , G06F12/0817
摘要： In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，一种方法包括在处理器核心中接收用于解码的指令，并且基于是否预测争用来动态地处理具有多种行为之一的指令。 如果没有预测到竞争，则在核心中执行指令，并且如果竞争是预测与指令相关联的数据被编组并发送到所选择的远程代理执行。 描述和要求保护其他实施例。
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公开(公告)号：US20100332801A1
公开(公告)日：2010-12-30
申请号：US12492652
申请日：2009-06-26
申请人： Joshua B. Fryman , Edward T. Grochowski , Toni Juan , Andrew Thomas Forsyth , John Mejia , Ramacharan Sundararaman , Eric Sprangle , Roger Espasa , Ravi Rajwar
发明人： Joshua B. Fryman , Edward T. Grochowski , Toni Juan , Andrew Thomas Forsyth , John Mejia , Ramacharan Sundararaman , Eric Sprangle , Roger Espasa , Ravi Rajwar
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3861 , G06F12/0817
摘要： In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，一种方法包括在处理器核心中接收用于解码的指令，并且基于是否预测争用来动态地处理具有多种行为之一的指令。 如果没有预测到竞争，则在核心中执行指令，并且如果竞争是预测与指令相关联的数据被编组并发送到所选择的远程代理执行。 描述和要求保护其他实施例。
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公开(公告)号：US08667250B2
公开(公告)日：2014-03-04
申请号：US11964631
申请日：2007-12-26
IPC分类号： G06F9/312
CPC分类号： G06F9/30025 , G06F9/30036 , G06F9/30043
摘要： A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.
摘要翻译： 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。
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公开(公告)号：US20130232318A1
公开(公告)日：2013-09-05
申请号：US13844111
申请日：2013-03-15
IPC分类号： G06F9/30
CPC分类号： G06F9/30025 , G06F9/30036 , G06F9/30043
摘要： A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.
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公开(公告)号：US20140019720A1
公开(公告)日：2014-01-16
申请号：US13762220
申请日：2013-02-07
IPC分类号： G06F9/30
CPC分类号： G06F9/30025 , G06F9/30036 , G06F9/30043
摘要： A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.
摘要翻译： 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。
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公开(公告)号：US20090172349A1
公开(公告)日：2009-07-02
申请号：US11964631
申请日：2007-12-26
IPC分类号： G06F9/30
CPC分类号： G06F9/30025 , G06F9/30036 , G06F9/30043
摘要： A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.
摘要翻译： 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。
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公开(公告)号：US20140052969A1
公开(公告)日：2014-02-20
申请号：US13976997
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3893
摘要： A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
摘要翻译： 描述处理核心，其具有执行单元逻辑电路，其具有第一寄存器以存储第一向量输入操作数，第二寄存器存储第二向量输入操作数和第三寄存器以存储包含标量输入操作数a，b的打包数据结构 ， C。 执行单元逻辑电路还包括执行操作的乘法器（a *（第一向量输入操作数））+（b *（第二向量操作数））+ c。
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公开(公告)号：US09792115B2
公开(公告)日：2017-10-17
申请号：US13976997
申请日：2011-12-23
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3893
摘要： A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
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10.发明授权Processor and system using a mask register to track progress of gathering and prefetching elements from memory 有权处理器和系统使用掩码寄存器跟踪从内存中采集和预取元素的进度公开(公告)号：US08892848B2
公开(公告)日：2014-11-18
申请号：US13175953
申请日：2011-07-05
申请人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
CPC分类号： G06F15/8069 , G06F9/30043 , G06F9/30047 , G06F9/30098 , G06F9/30101 , G06F9/345 , G06F9/383 , G06F12/02 , G06F12/0875 , G06F2212/452 , G06F2212/602 , G06F2212/6028
摘要： A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.
摘要翻译： 一种用于将值分配给第一寄存器中的元件的装置，系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段， 值可以指示相应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中每个数据域的值，并且为 第一寄存器中的每个数据字段具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。 描述和要求保护其他实施例。
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