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公开(公告)号：US20160119710A1
公开(公告)日：2016-04-28
申请号：US14920791
申请日：2015-10-22
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson , Dustin Dale Forman , Robert Lynn Blair , Peter John Frith
IPC: H04R1/10
CPC classification number: H04R1/1041 , H04M1/6058 , H04R5/04 , H04R2420/09
Abstract: An apparatus is disclosed for inputting digital data on the output channel(s) of an audio subsystem in an audio device, without interfering with normal operation of the audio subsystem. The described circuit includes a resistive element in parallel with the expected load device, such as a headphone or speaker. The resistive element receives a modulated digital signal from a data source or a switch, and the instantaneous current through the resistive element due to the modulated digital signal is reflected in a current feedback mechanism of the audio subsystem. Demodulation logic retrieves the digital signal from the current measured by the current feedback mechanism. A capacitor is provided to prevent the current in the resistive element from the digital signal from impacting the average DC current that the feedback mechanism uses to evaluate the load device.
Abstract translation: 公开了一种用于在音频设备中的音频子系统的输出通道上输入数字数据而不干扰音频子系统的正常操作的装置。 所描述的电路包括与期望的负载装置（例如耳机或扬声器）并联的电阻元件。 电阻元件从数据源或开关接收调制的数字信号，并且由于调制的数字信号引起的通过电阻元件的瞬时电流被反映在音频子系统的电流反馈机制中。 解调逻辑从当前反馈机制测量的电流中检索数字信号。 提供电容器以防止电阻元件中的电流数字信号影响反馈机构用于评估负载装置的平均DC电流。
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公开(公告)号：US08698660B2
公开(公告)日：2014-04-15
申请号：US13665801
申请日：2012-10-31
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson , Dustin Dale Forman
IPC: H03M3/00
Abstract: The present application describes an apparatus and method for improving the performance of ΣΔ modulators functioning as ADCs. In one embodiment, the ΣΔ modulator comprises a plurality of quantizers operating in a round-robin fashion, rather than the single quantizer of the prior art. The use of multiple quantizers allows the ΣΔ modulator to appear to be functioning at a significantly higher rate than a single quantizer allows. In another embodiment, a second-order ΣΔ modulator contains a plurality of control loops, rather than the single control loop of the prior art. The use of multiple control loops allows the ΣΔ modulator to have multiple points of maximum signal-to-noise ratio rather than a single such point as in prior art ΣΔ modulators.
Abstract translation: 本申请描述了一种用于提高＆Sgr＆amp; Dgr的性能的装置和方法; 作为ADC的调制器。 在一个实施例中，＆S＆amp; 调制器包括以循环方式操作的多个量化器，而不是现有技术的单个量化器。 使用多个量化器允许＆Sgr;＆Dgr; 调制器似乎以比单个量化器更高的速率运行。 在另一个实施例中，二阶＆S＆amp; 调制器包含多个控制回路，而不是现有技术的单个控制回路。 使用多个控制循环允许＆Sgr;＆Dgr; 调制器具有多个最大信噪比的点，而不是现有技术中的单个点;＆Dgr; 调制器
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公开(公告)号：US20130106486A1
公开(公告)日：2013-05-02
申请号：US13665801
申请日：2012-10-31
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson , Dustin Dale Forman
Abstract: The present application describes an apparatus and method for improving the performance of ΣΔ modulators functioning as ADCs. In one embodiment, the ΣΔ modulator comprises a plurality of quantizers operating in a round-robin fashion, rather than the single quantizer of the prior art. The use of multiple quantizers allows the ΣΔ modulator to appear to be functioning at a significantly higher rate than a single quantizer allows. In another embodiment, a second-order ΣΔ modulator contains a plurality of control loops, rather than the single control loop of the prior art. The use of multiple control loops allows the ΣΔ modulator to have multiple points of maximum signal-to-noise ratio rather than a single such point as in prior art ΣΔ modulators.
Abstract translation: 本申请描述了用于改善用作ADC的SigmaDelta调制器的性能的装置和方法。 在一个实施例中，SigmaDelta调制器包括以循环方式操作的多个量化器，而不是现有技术的单个量化器。 使用多个量化器可以使SigmaDelta调制器以比单个量化器允许的更高的速率运行。 在另一个实施例中，二阶SigmaDelta调制器包含多个控制回路，而不是现有技术的单个控制回路。 使用多个控制回路允许SigmaDelta调制器具有多个最大信噪比的点，而不是像现有技术的SigmaDelta调制器中的单个点。
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Patent Agency Ranking
公开(公告)号：US12224757B2
公开(公告)日：2025-02-11
申请号：US18117795
申请日：2023-03-06
Applicant: ESS Technology, Inc.
Inventor： Dustin Dale Forman , Libin Timothy George , Hassan Mohammadnavazi , Hu Jing Yao
Abstract: A method and apparatus for reducing jitter in a phase-locked loop (PLL). Clock signals provided to the PLL are resampled into the voltage domain of the VCO in the PLL rather than being merely level shifted into that voltage domain or input directly from digital domain clock dividers as in the prior art. The resampling is done with flip-flops in the analog domain using a faster synchronous clock in each case, and results in cleaner clock edges being presented to the PLL than those provided by the digital circuitry alone. A divided input clock signal is resampled using the undivided input clock, while a divided feedback clock signal is resampled using the feedback clock signal itself, i.e., the output of the VCO in the PLL. This removes jitter caused by the processing of clock signals in the digital voltage domain and thus reduces the jitter in the output signal.
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公开(公告)号：US20240305304A1
公开(公告)日：2024-09-12
申请号：US18117795
申请日：2023-03-06
Applicant: ESS Technology, Inc.
Inventor： Dustin Dale Forman , Libin Timothy George , Hassan Mohammadnavazi , Hu Jing Yao
CPC classification number: H03L7/091 , H03L7/0891 , H03L7/099
Abstract: A method and apparatus for reducing jitter in a phase-locked loop (PLL). Clock signals provided to the PLL are resampled into the voltage domain of the VCO in the PLL rather than being merely level shifted into that voltage domain or input directly from digital domain clock dividers as in the prior art. The resampling is done with flip-flops in the analog domain using a faster synchronous clock in each case, and results in cleaner clock edges being presented to the PLL than those provided by the digital circuitry alone. A divided input clock signal is resampled using the undivided input clock, while a divided feedback clock signal is resampled using the feedback clock signal itself, i.e., the output of the VCO in the PLL. This removes jitter caused by the processing of clock signals in the digital voltage domain and thus reduces the jitter in the output signal.
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公开(公告)号：US09462368B2
公开(公告)日：2016-10-04
申请号：US14920791
申请日：2015-10-22
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson , Dustin Dale Forman , Robert Lynn Blair , Peter John Frith
CPC classification number: H04R1/1041 , H04M1/6058 , H04R5/04 , H04R2420/09
Abstract: An apparatus is disclosed for inputting digital data on the output channel(s) of an audio subsystem in an audio device, without interfering with normal operation of the audio subsystem. The described circuit includes a resistive element in parallel with the expected load device, such as a headphone or speaker. The resistive element receives a modulated digital signal from a data source or a switch, and the instantaneous current through the resistive element due to the modulated digital signal is reflected in a current feedback mechanism of the audio subsystem. Demodulation logic retrieves the digital signal from the current measured by the current feedback mechanism. A capacitor is provided to prevent the current in the resistive element from the digital signal from impacting the average DC current that the feedback mechanism uses to evaluate the load device.
Abstract translation: 公开了一种用于在音频设备中的音频子系统的输出通道上输入数字数据而不干扰音频子系统的正常操作的装置。 所描述的电路包括与期望的负载装置（例如耳机或扬声器）并联的电阻元件。 电阻元件从数据源或开关接收调制的数字信号，并且由于调制的数字信号引起的通过电阻元件的瞬时电流被反映在音频子系统的电流反馈机制中。 解调逻辑从当前反馈机制测量的电流中检索数字信号。 提供电容器以防止电阻元件中的电流数字信号影响反馈机构用于评估负载装置的平均DC电流。
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公开(公告)号：US08994422B2
公开(公告)日：2015-03-31
申请号：US14055772
申请日：2013-10-16
Applicant: ESS Technology, Inc.
Inventor： Hu Jing Yao , Dustin Dale Forman , A. Martin Mallinson
Abstract: A method and system is disclosed in which the phase detector in a phase-locked loop is able to run at the fastest speed appropriate for a reference signal. A frequency offset is added to the output frequency of the phase-locked loop, to alter the frequency fed to the frequency divider which would receive the output frequency in a conventional PLL to an intermediate frequency. The frequency offset is selected so that the ratio of the intermediate frequency to the reference frequency is a simple fraction, and preferably an integer, i.e., the intermediate frequency is a multiple of the reference frequency. In cases where the relationship between the output frequency and the reference frequency is largely relatively prime, the phase detector is thus able to receive signals at the frequency of the reference signal and operate at the fastest speed appropriate for the reference signal.
Abstract translation: 公开了一种方法和系统，其中锁相环中的相位检测器能够以适合于参考信号的最快速度运行。 频率偏移被添加到锁相环的输出频率，以改变馈送到分频器的频率，该分频器将常规PLL中的输出频率接收到中频。 选择频率偏移，使得中频与参考频率的比率是简单的分数，优选地是整数，即中频是参考频率的倍数。 在输出频率和参考频率之间的关系很大程度上相对于素数的情况下，相位检测器因此能够以参考信号的频率接收信号并且以适合于参考信号的最快速度进行操作。
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公开(公告)号：US08773197B2
公开(公告)日：2014-07-08
申请号：US13683637
申请日：2012-11-21
Applicant: ESS Technology, Inc.
Inventor： Dustin Dale Forman , Trevor Blake Lynch-Staunton , Montana T. C. Reid
IPC: H03F3/38
CPC classification number: H03F3/217 , H03F1/3205 , H03F3/2171 , H03F3/2175
Abstract: The present application describes an apparatus and method for reducing distortion in a class-D amplifier. The power output section of the amplifier is driven by an adjusted PWM signal, rather than by a PWM signal created directly from the input analog signal. A reference output, designed to closely track the input analog signal, is compared to the amplifier output. The resulting difference is an error signal which is inverted and summed with a second analog signal corresponding to the directly created PWM signal and changes the timing of the voltage transitions of the second analog signal. The changed voltage transitions are used to create the adjusted PWM signal. The inversion of the error signal causes negative feedback which results in the adjustment of the PWM signal being in a direction which reduces the error signal and thus the distortion of the amplifier.
Abstract translation: 本申请描述了用于减少D类放大器中的失真的装置和方法。 放大器的功率输出部分由调整后的PWM信号驱动，而不是直接由输入模拟信号产生的PWM信号驱动。 与输出模拟信号紧密跟踪的参考输出与放大器输出进行比较。 所产生的差异是将与直接产生的PWM信号对应的第二模拟信号反相并相加并且改变第二模拟信号的电压转换的定时的误差信号。 改变的电压转换用于创建调整后的PWM信号。 误差信号的反转引起负反馈，导致PWM信号的调整在减小误差信号的方向上，从而导致放大器的失真。
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