公开(公告)号：US5625838A

公开(公告)日：1997-04-29

申请号：US482474

申请日：1995-06-07

Applicant: Edward R. Caudel ,  Surendar S. Magar

Inventor： Edward R. Caudel ,  Surendar S. Magar

IPC: G06F9/302 ,  G06F15/78 ,  G06F13/10 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F15/7814 ,  G06F15/7842 ,  G06F15/786

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0- to -15 bit shifter with sign extension.

Abstract translation: 一种用于实时数字信号处理的系统采用具有单独的片上程序ROM和数据RAM的单片微机器件，具有用于程序和数据的单独的地址和数据路径。 外部程序地址总线允许在扩展模式下进行片外程序提取，外部数据总线返回操作码。 总线交换模块允许在特殊情况下在单独的内部程序和数据总线之间进行转移。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到-15位移位器。

公开(公告)号：US5615383A

公开(公告)日：1997-03-25

申请号：US474606

申请日：1995-06-07

Applicant: Edward R. Caudel ,  Surendar S. Magar

Inventor： Edward R. Caudel ,  Surendar S. Magar

IPC: G06F9/302 ,  G06F15/78 ,  G06F15/16

CPC classification number: G06F9/3001 ,  G06F15/7814 ,  G06F15/7842 ,  G06F15/786

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract translation: 一种用于实时数字信号处理的系统采用具有单独的片上程序ROM和数据RAM的单片微机器件，具有用于程序和数据的单独的地址和数据路径。 外部程序地址总线允许在扩展模式下进行片外程序提取，外部数据总线返回操作码。 总线交换模块允许在特殊情况下在单独的内部程序和数据总线之间进行转移。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器。

公开(公告)号：US4514801A

公开(公告)日：1985-04-30

申请号：US350954

申请日：1982-02-22

Applicant: Edward R. Caudel ,  Gary L. Swoboda ,  Surendar S. Magar ,  Kevin C. McDonough ,  Antony W. Leigh

Inventor： Edward R. Caudel ,  Gary L. Swoboda ,  Surendar S. Magar ,  Kevin C. McDonough ,  Antony W. Leigh

IPC: G06F9/312 ,  G06F9/30

CPC classification number: G06F9/3004

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data; however, the accumulator in the data path may be used as a program address source for table-read and table-write, for example. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances, such as accumulator addressing. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract translation: 一种用于实时数字信号处理的系统采用具有单独的片上程序ROM和数据RAM的单片微机器件，具有针对程序和数据的单独的地址和数据路径; 然而，例如，数据路径中的累加器可以用作表读和表写的程序地址源。 外部程序地址总线允许在扩展模式下进行片外程序提取，外部数据总线返回操作码。 总线交换模块允许在特殊情况下（例如累加器寻址）在单独的内部程序和数据总线之间进行传输。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器。

公开(公告)号：US4498135A

公开(公告)日：1985-02-05

申请号：US350957

申请日：1982-02-22

Applicant: Edward R. Caudel

Inventor： Edward R. Caudel

IPC: G06F5/01 ,  G06F7/50 ,  G06F7/52 ,  G06F7/575 ,  G06F11/267 ,  G06F15/78 ,  G06F9/26

CPC classification number: G06F7/5338 ,  G06F11/2236 ,  G06F15/786 ,  G06F5/015 ,  G06F7/503 ,  G06F7/5095 ,  G06F7/575 ,  G06F2207/3872

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data; however, the accumulator in the data path may be used as a program address source for table look-up, for example. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances, such as accumulator addressing. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract translation: 一种用于实时数字信号处理的系统采用具有单独的片上程序ROM和数据RAM的单片微机器件，具有针对程序和数据的单独的地址和数据路径; 然而，例如，数据路径中的累加器可以用作表查找的程序地址源。 外部程序地址总线允许在扩展模式下进行片外程序提取，外部数据总线返回操作码。 总线交换模块允许在特殊情况下（例如累加器寻址）在单独的内部程序和数据总线之间进行传输。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器。

公开(公告)号：US4147984A

公开(公告)日：1979-04-03

申请号：US791616

申请日：1977-04-27

Applicant: Edward R. Caudel ,  William R. Wilson ,  Thomas E. Merrow

Inventor： Edward R. Caudel ,  William R. Wilson ,  Thomas E. Merrow

IPC: H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03H17/00 ,  H03L7/091 ,  H03L7/18 ,  H03L7/183 ,  H04B1/40 ,  H04W84/00

CPC classification number: H04W84/00 ,  H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03L7/091 ,  H03L7/183 ,  H04B1/40

Abstract: A transceiver includes a keyboard having a plurality of manually actuable keys for selecting operating modes and channels for operating thereon. A first digital processor has inputs coupled to the keyboard for receiving logic signals therefrom of a first format identifying the keys which are manually actuated. In response thereto, the first digital processor generates bit serial messages of a second format indicating the manually chosen operating mode and channel. A second digital processor has inputs coupled to receive the bit serial messages. In response thereto, the second digital processor generates a plurality of micro commands. A clocking signal generator circuit and switching circuit are coupled to receive the micro commands to control the transceiver.

Abstract translation: 收发器包括具有多个可手动致动的键的键盘，用于选择用于在其上操作的操作模式和通道。 第一数字处理器具有耦合到键盘的输入，用于从其接收标识手动启动的键的第一格式的逻辑信号。 响应于此，第一数字处理器生成指示手动选择的操作模式和通道的第二格式的位串行消息。 第二数字处理器具有耦合以接收位串行消息的输入。 响应于此，第二数字处理器产生多个微指令。 时钟信号发生器电路和开关电路被耦合以接收微指令以控制收发器。

公开(公告)号：US4145655A

公开(公告)日：1979-03-20

申请号：US791611

申请日：1977-04-27

Applicant: Edward R. Caudel ,  William R. Wilson

Inventor： Edward R. Caudel ,  William R. Wilson

IPC: H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03H17/00 ,  H03L7/091 ,  H03L7/18 ,  H03L7/183 ,  H04B1/40 ,  H04W84/00 ,  H04B1/38

CPC classification number: H04W84/00 ,  H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03L7/091 ,  H03L7/183 ,  H04B1/40

Abstract: A transceiver has digital transmitting capability. The transceiver includes an antenna having an input for transmitting signals applied thereto. Signal generating means generate first and second signals having first and second frequencies, and transmission means selectively couple the first and second signals to the antenna input in response to first and second micro commands respectively. A processor receives manually chosen messages for transmission comprised of a series of binary encoded symbols. In response thereto, the processor sequentially generates for a predetermined time interval the first micro command for each one bit and the second micro command for each zero bit to be transmitted.

Abstract translation: 收发器具有数字传输能力。 收发器包括具有用于发送施加到其上的信号的输入的天线。 信号发生装置产生具有第一和第二频率的第一和第二信号，并且传输装置分别响应于第一和第二微指令选择性地将第一和第二信号耦合到天线输入端。 处理器接收手动选择的用于传输的消息，其包括一系列二进制编码符号。 响应于此，处理器按照预定的时间间隔顺序产生每一位的第一微指令和要发送的每个零位的第二微指令。

公开(公告)号：US5854907A

公开(公告)日：1998-12-29

申请号：US272729

申请日：1994-07-08

Applicant: Edward R. Caudel ,  Surendar S. Magar

Inventor： Edward R. Caudel ,  Surendar S. Magar

IPC: G06F9/302 ,  G06F9/38 ,  G06F15/78 ,  G06F13/36

CPC classification number: G06F9/3001 ,  G06F15/7814 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/3802

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract translation: 一种用于实时数字信号处理的系统采用具有单独的片上程序ROM和数据RAM的单片微机器件，具有用于程序和数据的单独的地址和数据路径。 外部程序地址总线允许在扩展模式下进行片外程序提取，外部数据总线返回操作码。 总线交换模块允许在特殊情况下在单独的内部程序和数据总线之间进行转移。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器。

公开(公告)号：US5828896A

公开(公告)日：1998-10-27

申请号：US938166

申请日：1997-09-26

Applicant: Edward R. Caudel ,  Surendar S. Magar

Inventor： Edward R. Caudel ,  Surendar S. Magar

IPC: G06F9/302 ,  G06F9/38 ,  G06F15/78 ,  G06F15/00

CPC classification number: G06F9/3001 ,  G06F15/7842 ,  G06F9/3802

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

公开(公告)号：US5826111A

公开(公告)日：1998-10-20

申请号：US490445

申请日：1995-06-07

Applicant: Edward R. Caudel ,  Surendar S. Magar

Inventor： Edward R. Caudel ,  Surendar S. Magar

IPC: G06F9/302 ,  G06F9/38 ,  G06F15/78 ,  G06F3/05

CPC classification number: G06F9/3001 ,  G06F15/7814 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/3802

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device (10) having separate on-chip program ROM (14) and data RAM (15), with separate address and data paths for program and data. An external program address bus (RA) allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus (D). A bus interchange module (BIM) allows transfer between the separate internal program and data busses (P-Bus and D-Bus) in special circumstances. The internal busses are 16-bit, while the ALU and accumulator (Acc) are 32-bit. A multiplier circuit (M) produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter (S) with sign extension.

Abstract translation: 一种用于实时数字信号处理的系统采用具有单独的片上程序ROM（14）和数据RAM（15）的单片微机设备（10），具有用于程序和数据的单独的地址和数据路径。 外部程序地址总线（RA）允许以扩展模式进行片外程序提取，外部数据总线（D）返回操作码。 总线交换模块（BIM）允许在特殊情况下在单独的内部程序和数据总线（P-Bus和D-Bus）之间进行传输。 内部总线为16位，ALU和累加器（Acc）为32位。 乘法器电路（M）产生与ALU分离的单一状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器（S）。

公开(公告)号：US4349894A

公开(公告)日：1982-09-14

申请号：US210079

申请日：1980-11-24

Applicant: Edward R. Caudel

Inventor： Edward R. Caudel

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/40

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L27/1104

Abstract: An MOS memory cell of the static type employs a pair of cross-coupled driver transistors forming a bistable circuit, with load resistors replaced by a pair of series coupling transistors connecting storage nodes to complementary precharged data lines. A two phase clock turns on the coupling transistors in sequence, for refresh, so an intermediate node is charged during a first phase and discharged into the storage nodes during the second phase. Both transistors are turned on at the same time for read or write operations.

Abstract translation: 静态的MOS存储单元采用一对形成双稳态电路的交叉耦合驱动晶体管，其负载电阻由一对连接存储节点到互补预充电数据线的串联耦合晶体管代替。 两相时钟顺序地接通耦合晶体管，以便刷新，因此中间节点在第一阶段期间被充电并在第二阶段期间被放电到存储节点中。 两个晶体管同时导通以进行读取或写入操作。