公开(公告)号：US6000025A

公开(公告)日：1999-12-07

申请号：US938283

申请日：1997-09-26

Applicant: Edward R. Caudel ,  Surendar S. Magar

Inventor： Edward R. Caudel ,  Surendar S. Magar

IPC: G06F9/302 ,  G06F9/38 ,  G06F15/78 ,  G06F13/00

CPC classification number: G06F9/3001 ,  G06F15/7814 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/3802

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract translation: 一种用于实时数字信号处理的系统采用具有单独的片上程序ROM和数据RAM的单片微机器件，具有用于程序和数据的单独的地址和数据路径。 外部程序地址总线允许在扩展模式下进行片外程序提取，外部数据总线返回操作码。 总线交换模块允许在特殊情况下在单独的内部程序和数据总线之间进行转移。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器。

公开(公告)号：US4161697A

公开(公告)日：1979-07-17

申请号：US791449

申请日：1977-04-27

Applicant: Michael J. Cochran ,  Edward R. Caudel

Inventor： Michael J. Cochran ,  Edward R. Caudel

IPC: H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03H17/00 ,  H03L7/091 ,  H03L7/18 ,  H03L7/183 ,  H04B1/40 ,  H04W84/00 ,  H04B1/16

CPC classification number: H04W84/00 ,  H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03L7/091 ,  H03L7/183 ,  H04B1/40

Abstract: A radio receiver receives input signals comprised of a plurality of frequency bands lying respectively within a plurality of non-overlapping frequency channels. The signals include an itermittently present reference frequency signal. The radio receiver includes an autolock circuit for measuring the frequency of the intermittently present carrier and for generating digital signals indicating its frequency. A digital processor has inputs coupled to receive the digital signals for calculating in response thereto a selectable demodulating frequency dependent upon the frequency of the intermittently present carrier.

Abstract translation: 无线电接收机接收由分别位于多个非重叠频率信道中的多个频带组成的输入信号。 这些信号包括本地参考频率信号。 无线电接收机包括用于测量间歇存在载波的频率并产生指示其频率的数字信号的自动锁定电路。 数字处理器具有输入，其耦合以接收数字信号，以响应于此而计算取决于间歇性存在载波的频率的可选解调频率。

公开(公告)号：US3991305A

公开(公告)日：1976-11-09

申请号：US525236

申请日：1974-11-19

Applicant: Edward R. Caudel ,  Joseph H. Raymond, Jr.

Inventor： Edward R. Caudel ,  Joseph H. Raymond, Jr.

IPC: G01R31/28 ,  G06F3/02 ,  G06F3/023 ,  G06F11/22 ,  G06F15/02 ,  G06F15/78 ,  G11C11/402 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H03M11/20 ,  G06F3/14 ,  G06K15/18

CPC classification number: G11C11/402

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a data storage RAM, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. Input and output terminals are provided, as for keyboard input and display output. The operation is digit oriented in that an instruction accesses one digit of the RAM. One set of output terminals may be used for sequentially scanning the display digits and keyboard matrix; several of these may be actuated in any order or code combination, so the same terminals may be used to address an auxiliary RAM or drive a printer. Another set of output terminals may provide the segment outputs to the display. The two sets of output terminals are separately controllable. The data to both sets of output terminals is latched, so the machine can execute other instructions while a given output subsists.

Abstract translation: 用于提供电子计算器或数字处理器的功能的MOS / LSI半导体芯片包括数据存储RAM，用于程序指令存储的ROM，用于对数据执行操作的算术单元和用于定义机器的功能的控制电路 响应ROM中的指令以及机器中的条件和外部输入。 提供输入和输出端子，如键盘输入和显示输出。 操作是数字定向的，因为指令访问RAM的一位数字。 可以使用一组输出端子来顺序地扫描显示数字和键盘矩阵; 其中几个可以以任何顺序或代码组合来启动，因此可以使用相同的终端来寻址辅助RAM或驱动打印机。 另一组输出端子可以向显示器提供段输出。 两组输出端子可分开控制。 两组输出端子的数据被锁存，因此当给定的输出存在时，机器可以执行其他指令。

公开(公告)号：US5581792A

公开(公告)日：1996-12-03

申请号：US434173

申请日：1995-05-01

Applicant: Edward R. Caudel ,  Surendar S. Magar

Inventor： Edward R. Caudel ,  Surendar S. Magar

IPC: G06F9/302 ,  G06F15/78 ,  G06F9/24 ,  G06F15/16

CPC classification number: G06F9/3001 ,  G06F15/7814 ,  G06F15/7842 ,  G06F15/786

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device (10) having separate on-chip program ROM (14) and data RAM (15), with separate address and data paths for program and data. An external program address bus (RA) allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus (D). A bus interchange module (BIM) allows transfer between the separate internal program and data buses (P-Bus and D-Bus) in special circumstances. The internal buses are 16-bit, while the ALU and accumulator (Acc) are 32-bit. A multiplier circuit (M) produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter (S) with sign extension.

Abstract translation: 一种用于实时数字信号处理的系统采用具有单独的片上程序ROM（14）和数据RAM（15）的单片微机设备（10），具有用于程序和数据的单独的地址和数据路径。 外部程序地址总线（RA）允许以扩展模式进行片外程序提取，外部数据总线（D）返回操作码。 总线交换模块（BIM）允许在特殊情况下在单独的内部程序和数据总线（P-Bus和D-Bus）之间进行传输。 内部总线为16位，ALU和累加器（Acc）为32位。 乘法器电路（M）产生与ALU分离的单一状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器（S）。

公开(公告)号：US4608634A

公开(公告)日：1986-08-26

申请号：US350956

申请日：1982-02-22

Applicant: Edward R. Caudel ,  Surendar S. Magar ,  Wanda K. Gass

Inventor： Edward R. Caudel ,  Surendar S. Magar ,  Wanda K. Gass

IPC: G06F7/544 ,  G06F15/78 ,  G06F9/00 ,  G06F13/00

CPC classification number: G06F7/5443 ,  G06F15/7857 ,  G06F7/49921 ,  G06F7/49994

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data; however, the accumulator in the data path may be used as a program address source. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. A separate shift or offset is provided in coupling the output of the accumulator to an internal data bus for use in scaling when storing the accumulator contents in internal data RAM specified by instructions. Also, the RAM itself has an internal shift function used in convolution.

Abstract translation: 一种用于实时数字信号处理的系统采用具有单独的片上程序ROM和数据RAM的单片微机器件，具有针对程序和数据的单独的地址和数据路径; 然而，数据路径中的累加器可以用作程序地址源。 外部程序地址总线允许在扩展模式下进行片外程序提取，外部数据总线返回操作码。 总线交换模块允许在单独的内部程序和数据总线之间进行传输。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器。 当将累加器内容存储在由指令指定的内部数据RAM中时，将累加器的输出耦合到内部数据总线以用于缩放，提供单独的移位或偏移。 此外，RAM本身具有用于卷积的内部移位功能。

公开(公告)号：US4586131A

公开(公告)日：1986-04-29

申请号：US654572

申请日：1984-09-26

Applicant: Edward R. Caudel ,  Surendar S. Magar ,  Antony W. Leigh

Inventor： Edward R. Caudel ,  Surendar S. Magar ,  Antony W. Leigh

IPC: G06F15/78 ,  G06F15/00

CPC classification number: G06F15/786

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The data RAM has an internal shift arrangement useful in processing convolution algorithms. An addressed location in the RAM is read out and also shifted to the next higher location in one instruction cycle.

Abstract translation: 一种用于实时数字信号处理的系统采用具有单独的片上程序ROM和数据RAM的单片微机器件，具有用于程序和数据的单独的地址和数据路径。 外部程序地址总线允许在扩展模式下进行片外程序提取，外部数据总线返回操作码。 总线交换模块允许在特殊情况下在单独的内部程序和数据总线之间进行转移。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器。 数据RAM具有用于处理卷积算法的内部移位布置。 读出RAM中的寻址位置，并在一个指令周期内移位到下一个更高的位置。

公开(公告)号：US4533992A

公开(公告)日：1985-08-06

申请号：US350959

申请日：1982-02-22

Applicant: Surendar S. Magar ,  Edward R. Caudel

Inventor： Surendar S. Magar ,  Edward R. Caudel

IPC: G06F5/01 ,  G06F7/38

CPC classification number: G06F5/015

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract translation: 一种用于实时数字信号处理的系统采用具有单独的片上程序ROM和数据RAM的单片微机器件，具有用于程序和数据的单独的地址和数据路径。 外部程序地址总线允许在扩展模式下进行片外程序提取，外部数据总线返回操作码。 总线交换模块允许在特殊情况下在单独的内部程序和数据总线之间进行转移。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器。

公开(公告)号：US4491910A

公开(公告)日：1985-01-01

申请号：US350951

申请日：1982-02-22

Applicant: Edward R. Caudel ,  Surendar S. Magar ,  Antony W. Leigh

Inventor： Edward R. Caudel ,  Surendar S. Magar ,  Antony W. Leigh

IPC: G06F15/78 ,  G06F9/22 ,  G06F13/00

CPC classification number: G06F15/786

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The data RAM has an internal shift arrangement useful in processing convolution algorithms. An addressed location in the RAM is read out and also shifted to the next higher location in one instruction cycle.

Abstract translation: 一种用于实时数字信号处理的系统采用具有单独的片上程序ROM和数据RAM的单片微机器件，具有用于程序和数据的单独的地址和数据路径。 外部程序地址总线允许在扩展模式下进行片外程序提取，外部数据总线返回操作码。 总线交换模块允许在特殊情况下在单独的内部程序和数据总线之间进行转移。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器。 数据RAM具有用于处理卷积算法的内部移位布置。 读出RAM中的寻址位置，并在一个指令周期内移位到下一个更高的位置。

公开(公告)号：US3938094A

公开(公告)日：1976-02-10

申请号：US392405

申请日：1973-08-28

Applicant: Edward R. Caudel

Inventor： Edward R. Caudel

IPC: G06F7/50 ,  G06F7/501 ,  G06F13/18 ,  G06F13/40 ,  G06F13/42 ,  G06F13/00

CPC classification number: G06F7/501 ,  G06F13/18 ,  G06F13/4077 ,  G06F13/4243 ,  G06F2207/3872

Abstract: A single parallel bus interconnects the various portions of a central processing unit. Data transmission between the various portions of the processor is based on sequential use of the common bus, and is synchronized by control circuitry. Circuit means are included for providing access of the various portions of the processor to the bus, and includes means for generating data on the bus for transmission, and for detecting data transmitted by the bus. To minimize access time to the bus whenever data is to be transmitted, means are provided for precharging the bus to a reference potential and then selectively discharging the bus to correspond to the data to be transmitted. In a different aspect of the invention a common bus is used to transmit data between the processor and computing equipment separate from the processor. In this aspect of the invention, circuitry is provided for detecting current on the bus corresponding to data, and for amplifying this current to a suitable level, and then generating a voltage suitable for transmission by the bus.

Abstract translation: 单个并行总线将中央处理单元的各个部分互连。 处理器各部分之间的数据传输是基于公共总线的顺序使用，并由控制电路同步。 包括用于提供处理器的各个部分到总线的访问的电路装置，并且包括用于在总线上生成用于传输的数据并用于检测由总线发送的数据的装置。 为了最小化数据传输时对总线的访问时间，提供了用于将总线预充电到参考电位的装置，然后选择性地对总线进行放电以对应于待发送的数据。 在本发明的另一方面，公共总线用于在处理器和与处理器分开的计算设备之间传输数据。 在本发明的这个方面，提供电路用于检测与数据相对应的总线上的电流，并且用于将该电流放大到合适的电平，然后产生适于由总线传输的电压。

公开(公告)号：US6108765A

公开(公告)日：2000-08-22

申请号：US947064

申请日：1997-10-08

Applicant: Edward R. Caudel ,  Surendar S. Magar

Inventor： Edward R. Caudel ,  Surendar S. Magar

IPC: G06F9/302 ,  G06F15/78 ,  G06F13/00

CPC classification number: G06F9/3001 ,  G06F15/7814 ,  G06F15/7842 ,  G06F15/786

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device (10) having separate on-chip program ROM (14) and data RAM (15), with separate address and data paths for program and data. An external program address bus (RA) allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus (D). A bus interchange module (BIM) allows transfer between the separate internal program and data busses (P-Bus and D-Bus) in special circumstances. The internal busses are 16-bit, while the ALU and accumulator (Acc) are 32-bit. A multiplier circuit (M) produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter (S) with sign extension.

Abstract translation: 一种用于实时数字信号处理的系统采用具有单独的片上程序ROM（14）和数据RAM（15）的单片微机设备（10），具有用于程序和数据的单独的地址和数据路径。 外部程序地址总线（RA）允许以扩展模式进行片外程序提取，外部数据总线（D）返回操作码。 总线交换模块（BIM）允许在特殊情况下在单独的内部程序和数据总线（P-Bus和D-Bus）之间进行传输。 内部总线为16位，ALU和累加器（Acc）为32位。 乘法器电路（M）产生与ALU分离的单一状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器（S）。