公开(公告)号：US10008155B2

公开(公告)日：2018-06-26

申请号：US15220713

申请日：2016-07-27

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ,  University-Industry Cooperation Group of Kyung Hee Univ

Inventor： Chunwon Byun ,  Jong-Heon Yang ,  Sung-Min Yoon ,  Kyoung Ik Cho ,  Chi-Sun Hwang

IPC: G09G3/12 ,  G09G3/3266 ,  G09G3/3233

CPC classification number: G09G3/3266 ,  G09G3/3233 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2330/021 ,  G09G2330/028

Abstract: Provided is a gate driving circuit. The gate driving circuit includes an ith modulation circuit and an ith line selection circuit (where i is a natural number greater than 1). The ith modulation circuit outputs an ith modulation voltage to an ith line selection circuit based on received first to third control signals. The ith line selection circuit includes a memory transistor that is turned on or turned off according to a level of the received ith modulation voltage.

公开(公告)号：US09728149B2

公开(公告)日：2017-08-08

申请号：US15007856

申请日：2016-01-27

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Chunwon Byun ,  Jae-Eun Pi ,  Kyoung Ik Cho ,  Hye Yong Chu ,  Chi-Sun Hwang

IPC: G09G3/36 ,  G09G3/3233

CPC classification number: G09G3/3648 ,  G09G3/3233 ,  G09G2300/023 ,  G09G2300/046 ,  G09G2300/0842

Abstract: A display panel includes pixels connected to each of gate lines and data lines. Each of the pixels includes a first transistor connected between a corresponding data line among the data lines and a first node and configured to deliver a data signal of the corresponding data line to the first node in response to an input signal received through a corresponding gate line among the gate lines, a reflective element circuit connected to the first node, and configured to implement the reflective mode in response to a signal of the first node when a first mode selection signal indicates a reflective mode, an emissive element circuit connected to a second node, and configured to implement the emissive mode in response to the signal of the first node when the mode selection mode indicates an emissive mode.

公开(公告)号：US09634120B2

公开(公告)日：2017-04-25

申请号：US14610410

申请日：2015-01-30

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Kyoung Ik Cho ,  Jae Bon Koo ,  Chan Woo Park ,  Bock Soon Na ,  Sang Seok Lee ,  Sang Chul Lim ,  Soon-Won Jung ,  Hye Yong Chu

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L21/3105

CPC classification number: H01L29/78603 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31144 ,  H01L27/1218 ,  H01L27/1266 ,  H01L29/66742

Abstract: Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.

公开(公告)号：US08653631B2

公开(公告)日：2014-02-18

申请号：US13775280

申请日：2013-02-25

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jae Bon Koo ,  Jong-Hyun Ahn ,  Seung Youl Kang ,  Hasan Musarrat ,  In-Kyu You ,  Kyoung Ik Cho

IPC: H01L29/06

CPC classification number: H01L27/1266 ,  H01L27/1214 ,  H01L27/1218 ,  H01L29/78603

Abstract: Provided are a transferred thin film transistor and a method of manufacturing the same. The method includes: forming a source region and a drain region that extend in a first direction in a first substrate and a channel region between the source region and the drain region; forming trenches that extend in a second direction in the first substrate to define an active layer between the trenches, the second direction intersecting the first direction; separating the active layer between the trenches from the first substrate by performing an anisotropic etching process on the first substrate inside the trenches; attaching the active layer on a second substrate; and forming a gate electrode in the first direction on the channel region of the active layer.

Abstract translation: 提供了一种转移的薄膜晶体管及其制造方法。 该方法包括：形成在第一衬底中沿第一方向延伸的源极区域和漏极区域以及源极区域和漏极区域之间的沟道区域; 形成在所述第一衬底中沿第二方向延伸的沟槽，以在所述沟槽之间限定有源层，所述第二方向与所述第一方向相交; 通过在所述沟槽内的所述第一衬底上进行各向异性蚀刻工艺，从所述第一衬底分离所述沟槽之间的有源层; 将活性层附着在第二基底上; 以及在有源层的沟道区上沿第一方向形成栅电极。