公开(公告)号：US08298895B1

公开(公告)日：2012-10-30

申请号：US13285282

申请日：2011-10-31

申请人： Emre Alptekin

发明人： Emre Alptekin

IPC分类号： H01L21/336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L29/0684 ,  H01L29/1041 ,  H01L29/66537

摘要： In a replacement metal gate process flow, sacrificial gates are exposed and removed subsequent to the formation of source and drain regions for various transistor devices. Sidewalls formed adjacent to the sacrificial gates remain. By using an angled implant such that, for a short-channel device, the remaining sidewalls shadow and protect the exposed short-channel region, a designer may adjust the threshold voltage on long-channel devices without affecting the threshold voltage of the short-channel device.

摘要翻译： 在替代的金属栅极工艺流程中，在形成用于各种晶体管器件的源极和漏极区域之后，牺牲栅极被暴露和去除。 与牺牲栅相邻形成的侧壁保留。 通过使用成角度的植入物，使得对于短通道器件，剩余的侧壁阴影并保护暴露的短沟道区域，设计者可以调整长沟道器件上的阈值电压而不影响短沟道的阈值电压 设备。

公开(公告)号：US10103226B2

公开(公告)日：2018-10-16

申请号：US13459278

申请日：2012-04-30

申请人： Reinaldo A. Vega ,  Emre Alptekin ,  Hung H. Tran ,  Xiaobin Yuan

发明人： Reinaldo A. Vega ,  Emre Alptekin ,  Hung H. Tran ,  Xiaobin Yuan

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L21/28

摘要： A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials.

公开(公告)号：US08853862B2

公开(公告)日：2014-10-07

申请号：US13330817

申请日：2011-12-20

申请人： Emre Alptekin ,  Reinaldo Vega

发明人： Emre Alptekin ,  Reinaldo Vega

IPC分类号： H01L21/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/311

CPC分类号： H01L29/665 ,  H01L21/28525 ,  H01L21/76804 ,  H01L21/76889 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a first and a second transistor; a second epitaxial-grown region directly on top of the first epitaxial-grown region with the second epitaxial-grown region having a width that is wider than that of the first epitaxial-grown region; and a silicide region formed on a top portion of the second epitaxial-grown region with the silicide region having an interface, with rest of the second epitaxial-grown region, that is wider than that of the first epitaxial-grown region. In one embodiment, the second epitaxial-grown region is at a level above a top surface of the first and second gates of the first and second transistors.

摘要翻译： 本发明的实施例提供一种用于晶体管的接触结构。 接触结构包括分别在第一和第二晶体管的第一和第二栅极之间的第一外延生长区域; 第二外延生长区域直接在第一外延生长区域的顶部上，第二外延生长区域的宽度比第一外延生长区域的宽度宽; 以及形成在所述第二外延生长区域的顶部上的硅化物区域，其中所述硅化物区域具有与所述第一外延生长区域相比更接近所述第二外延生长区域的其余部分的界面。 在一个实施例中，第二外延生长区域处于第一和第二晶体管的第一和第二栅极的顶表面上方的水平。

公开(公告)号：US20130285138A1

公开(公告)日：2013-10-31

申请号：US13459278

申请日：2012-04-30

申请人： Reinaldo A. Vega ,  Emre Alptekin ,  Hung H. Tran ,  Xiaobin Yuan

发明人： Reinaldo A. Vega ,  Emre Alptekin ,  Hung H. Tran ,  Xiaobin Yuan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0684 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/78

摘要： A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials.

摘要翻译： 制造隧道场效应晶体管（TFET）的方法包括在由外延生长的源材料覆盖的衬底上形成由侧壁间隔物包围的虚拟栅极堆叠; 形成掺杂源极和漏极区域，随后形成围绕侧壁间隔物的层间电介质; 去除虚拟栅极堆叠，蚀刻自对准腔; 在自对准蚀刻腔内外延生长薄沟道区; 在自对准的蚀刻腔内共形沉积栅极电介质和金属栅极材料; 并且平坦化替代金属栅极堆叠的顶表面以去除栅极电介质和金属栅极材料的残留物。

公开(公告)号：US08492275B2

公开(公告)日：2013-07-23

申请号：US13186519

申请日：2011-07-20

申请人： Emre Alptekin ,  Viraj Y. Sardesai ,  Cung D. Tran ,  Bin Yang

发明人： Emre Alptekin ,  Viraj Y. Sardesai ,  Cung D. Tran ,  Bin Yang

IPC分类号： H01L21/44

CPC分类号： H01L23/485 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/76814 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.

摘要翻译： 方法通过在衬底内和/或衬底上形成多个器件的至少一部分形成集成电路结构，并且在邻近器件的衬底上的层间电介质层中图案化沟槽。 图案形成相对较窄的沟槽和较宽的沟槽。 然后，所述方法对沟槽进行补偿材料的成角度注入。 成角度的植入物的角度相对于在较窄沟槽的底部注入衬底的区域中的补偿材料的量，在较宽沟槽底部的衬底区域中植入更大浓度的补偿材料。 然后，该方法将金属材料沉积在沟槽内，并加热金属材料以从金属材料形成硅化物。

公开(公告)号：US20130069124A1

公开(公告)日：2013-03-21

申请号：US13237732

申请日：2011-09-20

申请人： Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

发明人： Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/6659 ,  H01L29/7833

摘要： An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

摘要翻译： 提供具有均匀厚度的硅化物层的MOSFET器件及其制造方法。 一种这样的方法包括在硅半导体衬底的表面上的宽且窄的接触沟槽上沉积金属层。 在金属/硅界面处形成均匀薄的无定形混合合金层时，除去过量的（未反应的）金属。 该器件被退火以促进在衬底表面上形成薄的硅化物层，其在宽和窄接触沟槽的底部显示均匀的厚度。

公开(公告)号：US08652963B2

公开(公告)日：2014-02-18

申请号：US13237732

申请日：2011-09-20

申请人： Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

发明人： Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

IPC分类号： H01L21/44

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/6659 ,  H01L29/7833

摘要： An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

摘要翻译： 提供具有均匀厚度的硅化物层的MOSFET器件及其制造方法。 一种这样的方法包括在硅半导体衬底的表面上的宽且窄的接触沟槽上沉积金属层。 在金属/硅界面处形成均匀薄的无定形混合合金层时，除去过量的（未反应的）金属。 该器件被退火以促进在衬底表面上形成薄的硅化物层，其在宽和窄接触沟槽的底部显示均匀的厚度。

公开(公告)号：US08603915B2

公开(公告)日：2013-12-10

申请号：US13305122

申请日：2011-11-28

申请人： Emre Alptekin ,  Ahmet S. Ozcan ,  Viraj Y. Sardesai ,  Cung D. Tran

发明人： Emre Alptekin ,  Ahmet S. Ozcan ,  Viraj Y. Sardesai ,  Cung D. Tran

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76897

摘要： A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices.

摘要翻译： 描述了一种多级硅化工艺，其中用于暴露接触区域的电介质蚀刻被定时以对于最高的接触区域是最佳的。 在暴露最高的接触区域之后，在暴露的接触区域上形成硅化物，并且对所形成的硅化物进行选择性地再次蚀刻电介质以暴露低于最高接触区域的另一个接触区域，而不会使 最高的接触区域。 然后，该过程在下接触区域上形成硅化物。 该过程可能继续变化深度。 在不使用附加掩蔽步骤的情况下执行每个后续蚀刻。 通过操纵现有硅化物和沉积金属的扩散性能，形成在具有不同深度/高度的接触区域上的硅化物可以包含不同的组成，并针对不同的极性器件如nFET和pFET器件进行优化。

公开(公告)号：US20130154026A1

公开(公告)日：2013-06-20

申请号：US13330817

申请日：2011-12-20

申请人： Emre Alptekin ,  Reinaldo Vega

发明人： Emre Alptekin ,  Reinaldo Vega

IPC分类号： H01L27/088 ,  H01L21/768

CPC分类号： H01L29/665 ,  H01L21/28525 ,  H01L21/76804 ,  H01L21/76889 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a first and a second transistor; a second epitaxial-grown region directly on top of the first epitaxial-grown region with the second epitaxial-grown region having a width that is wider than that of the first epitaxial-grown region; and a silicide region formed on a top portion of the second epitaxial-grown region with the silicide region having an interface, with rest of the second epitaxial-grown region, that is wider than that of the first epitaxial-grown region. In one embodiment, the second epitaxial-grown region is at a level above a top surface of the first and second gates of the first and second transistors.

摘要翻译： 本发明的实施例提供一种用于晶体管的接触结构。 接触结构包括分别在第一和第二晶体管的第一和第二栅极之间的第一外延生长区域; 第二外延生长区域直接在第一外延生长区域的顶部上，第二外延生长区域的宽度比第一外延生长区域的宽度宽; 以及形成在所述第二外延生长区域的顶部上的硅化物区域，其中所述硅化物区域具有与所述第一外延生长区域相比更接近所述第二外延生长区域的其余部分的界面。 在一个实施例中，第二外延生长区域处于第一和第二晶体管的第一和第二栅极的顶表面上方的水平。

公开(公告)号：US20130137260A1

公开(公告)日：2013-05-30

申请号：US13305122

申请日：2011-11-28

申请人： Emre Alptekin ,  Ahmet S. Ozcan ,  Viraj Y. Sardesai ,  Cung D. Tran

发明人： Emre Alptekin ,  Ahmet S. Ozcan ,  Viraj Y. Sardesai ,  Cung D. Tran

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76897

摘要： A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices.

摘要翻译： 描述了一种多级硅化工艺，其中用于暴露接触区域的电介质蚀刻被定时以对于最高的接触区域是最佳的。 在暴露最高的接触区域之后，在暴露的接触区域上形成硅化物，并且对所形成的硅化物进行选择性地再次蚀刻电介质以暴露低于最高接触区域的另一个接触区域，而不会使 最高的接触区域。 然后，该过程在下接触区域上形成硅化物。 该过程可能继续变化深度。 在不使用附加掩蔽步骤的情况下执行每个后续蚀刻。 通过操纵现有硅化物和沉积金属的扩散性能，形成在具有不同深度/高度的接触区域上的硅化物可以包含不同的组成，并针对不同的极性器件如nFET和pFET器件进行优化。