Method of error correction in a multi-bit-per-cell flash memory
    11.
    发明申请
    Method of error correction in a multi-bit-per-cell flash memory 有权
    多比特单元闪存中的纠错方法

    公开(公告)号:US20080010581A1

    公开(公告)日:2008-01-10

    申请号:US11607945

    申请日:2006-12-04

    IPC分类号: G11C29/00

    摘要: Data are encoded as a systematic or nonsystematic codeword that is stored in a memory such as a flash memory. A representation of the codeword is read from the memory. A plurality of bits related to the representation of the codeword is decoded iteratively. The plurality of bits could be, for example, part or all of the representation of the codeword itself or part or all of the results of preliminary processing of part or all of the representation of the codeword.

    摘要翻译: 数据被编码为存储在诸如闪存之类的存储器中的系统或非系统码字。 从存储器读取码字的表示。 与代码字的表示相关的多个位被迭代地解码。 多个比特可以是例如代码字本身的表示的部分或全部,或部分或全部代码字表示的初步处理结果的部分或全部。

    Error correction decoding by trial and error
    12.
    发明申请
    Error correction decoding by trial and error 有权
    纠错解码通过反复试验

    公开(公告)号:US20070283227A1

    公开(公告)日:2007-12-06

    申请号:US11528556

    申请日:2006-09-28

    IPC分类号: H03M13/00

    摘要: A representation of a codeword is decoded by applying a first decoder of the codeword to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword. Preferably, applying the first decoder consumes less power and is faster than applying the second decoder. Data are ported by encoding the data as a codeword, exporting the codeword to a corrupting medium, importing a representation of the codeword, and applying a first decoder to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword.

    摘要翻译: 通过将码字的第一解码器应用于码字的表示来解码码字的表示。 如果应用第一解码器不能解码码字的表示,则码字的第二解码器被应用于码字的表示。 优选地,应用第一解码器消耗较少的功率并且比应用第二解码器更快。 数据通过将数据编码为码字来移植,将码字导出到破坏性介质,导入码字的表示,以及将第一解码器应用于码字的表示。 如果应用第一解码器不能解码码字的表示,则码字的第二解码器被应用于码字的表示。

    Systems and methods of storing data
    15.
    发明授权
    Systems and methods of storing data 有权
    存储数据的系统和方法

    公开(公告)号:US08880977B2

    公开(公告)日:2014-11-04

    申请号:US13329684

    申请日:2011-12-19

    摘要: A method of writing data includes receiving a data page to be stored in a data storage device and initiating an encode operation to encode the data page. The encode operation generates first encoded data and a first portion of the first encoded data is stored to the first physical page of the data storage device. The method includes initiating storage of a second portion of the first encoded data to a second physical page of the data storage device. The method also includes initiating a decode operation to recover the data page. The decode operation uses a representation of the first portion of the first encoded data that is read from the first physical page without using any data from the second physical page.

    摘要翻译: 一种写入数据的方法包括:接收要存储在数据存储设备中的数据页,并启动对数据页进行编码的编码操作。 编码操作生成第一编码数据,并且第一编码数据的第一部分被存储到数据存储设备的第一物理页面。 该方法包括启动第一编码数据的第二部分的存储到数据存储设备的第二物理页面。 该方法还包括启动解码操作以恢复数据页面。 解码操作使用从第一物理页读取的第一编码数据的第一部分的表示,而不使用来自第二物理页的任何数据。

    Apparatus and method for enhancing flash endurance by encoding data
    16.
    发明授权
    Apparatus and method for enhancing flash endurance by encoding data 失效
    通过编码数据提高闪存耐久性的装置和方法

    公开(公告)号:US08756365B2

    公开(公告)日:2014-06-17

    申请号:US13148738

    申请日:2010-02-11

    IPC分类号: G06F12/00

    摘要: Input bits are stored in memory cells by mapping the input bits into a larger number of transformed bits using a shaping encoding that has a downward asymptotic bias with respect to a mapping of bit patterns to cell states and programming some of the cells according to that mapping of bit patterns to cell states. The programmed cells are erased before being programmed to store any other bits. The invention sacrifices memory capacity to increase endurance.

    摘要翻译: 通过使用相对于位模式对单元状态的映射具有向下渐近偏移的整形编码并根据该映射来编程一些单元,将输入位存储在存储器单元中,将输入位映射到更大数目的变换位中 的位模式到单元状态。 在被编程为存储任何其他位之前,编程的单元被擦除。 本发明牺牲记忆能力以增加耐力。

    Memory-efficient LDPC decoding
    17.
    发明授权
    Memory-efficient LDPC decoding 失效
    高效率的内存存储解码

    公开(公告)号:US08661310B2

    公开(公告)日:2014-02-25

    申请号:US13609984

    申请日:2012-09-11

    IPC分类号: H03M13/00

    CPC分类号: H03M13/114 H03M13/6505

    摘要: To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N−K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes.

    摘要翻译: 为了将编码K个信息比特的码字的表示解码为N个K个码字比特,消息在其中E个边缘连接比特节点和校验节点的图的N个比特节点和N-K个校验节点之间进行交换。 当消息被交换时,存储少于E个消息,和/或存储少于N个码字比特的软估计。 在一些实施例中,消息仅在子图中以及子图和一个或多个外部校验节点之间交换。 当消息被交换时,最大数量的存储消息是具有最多边缘的子图中的边数加上将子图连接到外部校验节点的边数,和/或最大 存储的软估计数是具有最多位节点的子图中的比特节点的数量。

    Fast detection of convergence or divergence in iterative decoding
    18.
    发明授权
    Fast detection of convergence or divergence in iterative decoding 失效
    快速检测迭代解码中的收敛或发散

    公开(公告)号:US08645810B2

    公开(公告)日:2014-02-04

    申请号:US13194952

    申请日:2011-07-31

    IPC分类号: H03M13/03

    CPC分类号: H03M13/1128

    摘要: A termination indication is computed during an iteration of an iterative decoding of a representation of a codeword according to a schedule. The termination indication is tested to see if the decoding has converged or is not likely to converge. The testing of the termination indication shows convergence or lack of likelihood thereof even if a codeword bit estimate was flipped during an immediately preceding traversal of the schedule. Preferably, the termination indication includes an error correction syndrome weight, a zero value whereof indicates convergence, and the computing of the termination indication includes, in response to the flipping of a codeword bit estimate, flipping the error correction syndrome bits that are influenced by that codeword bit estimate.

    摘要翻译: 在根据时间表对码字的表示的迭代解码的迭代期间计算终止指示。 测试终止指示以查看解码是否收敛或不可能收敛。 终止指示的测试显示出收敛或缺乏可能性,即使在紧接着的日程表遍历期间翻转了码字比特估计。 优选地,终止指示包括纠错综合征权重,其值指示收敛的零值,并且终止指示的计算响应于码字比特估计的翻转而包括翻转受该比特估计影响的纠错综合征比特 码字比特估计。

    Reading a flash memory by constrained decoding
    19.
    发明授权
    Reading a flash memory by constrained decoding 有权
    通过约束解码读取闪存

    公开(公告)号:US08464131B2

    公开(公告)日:2013-06-11

    申请号:US12645499

    申请日:2009-12-23

    IPC分类号: G06F11/00

    摘要: To read memory cells that have been programmed to store an ECC codeword, with each cell storing a respective plurality of bits of the codeword, a respective value of an operational parameter such as a threshold voltage of each cell is measured. Each bit is assigned a respective metric, such as a LLR estimate of the bit, based at least in part on the respective value of the operational parameter of the bit's cell. The metrics are decoded with reference both to the ECC and to mutual constraints of the metrics within each cell that are independent of the ECC.

    摘要翻译: 为了读取已编程为存储ECC码字的存储器单元,其中每个单元存储码字的相应多个位,测量诸如每个单元的阈值电压的操作参数的相应值。 至少部分地基于比特的小区的操作参数的相应值,为比特分配各个度量,例如比特的LLR估计。 参考ECC和与独立于ECC的每个单元内的度量的相互约束来对度量进行解码。

    Matrix structure for block encoding
    20.
    发明授权
    Matrix structure for block encoding 有权
    块编码的矩阵结构

    公开(公告)号:US08464123B2

    公开(公告)日:2013-06-11

    申请号:US12774746

    申请日:2010-05-06

    IPC分类号: H03M13/00

    摘要: A plurality of information bits are encoded using a parity-check matrix that is equivalent to a modular code matrix. The modular code matrix is a diagonal sub-matrix structure immediately above a connection layer that includes a plurality of diverse connection layer sub-matrices, all but at most one of which are below corresponding diagonal matrix structure sub-matrices. The information bits are assembled with a plurality of parity bits produced by the encoding to provide a codeword that is exported to a medium. Preferably, all the diagonal matrix structure sub-matrices are identical. Preferably, some of the parity bits are computed using only diagonal matrix structure sub-matrices.

    摘要翻译: 使用等同于模块代码矩阵的奇偶校验矩阵对多个信息位进行编码。 模块代码矩阵是紧邻连接层上方的对角子矩阵结构,其包括多个不同的连接层子矩阵,除了其中最多一个在相应的对角矩阵结构子矩阵之下。 信息比特与通过编码产生的多个奇偶校验位组合,以提供输出到介质的码字。 优选地,所有对角矩阵结构子矩阵是相同的。 优选地,使用仅对角矩阵结构子矩阵来计算一些奇偶校验位。