公开(公告)号：US06799263B1

公开(公告)日：2004-09-28

申请号：US09430361

申请日：1999-10-28

申请人： Dale C. Morris ,  James R. Callister ,  Stephen R. Undy

发明人： Dale C. Morris ,  James R. Callister ,  Stephen R. Undy

IPC分类号： G06F940

CPC分类号： G06F9/3802

摘要： A method for prefetching instructions into cache memory using a prefetch instruction. The prefetch instruction contains a target field, a count field, a cache level field, a flush field, and a trace field. The target field specifies the address at which prefetching begins. The count field specifies the number of instructions to prefetch. The flush field indicates whether earlier prefetches should be discarded and whether in-progress prefetches should be aborted. The level field specifies the level of the cache into which the instructions should be prefetched. The trace field establishes a trace vector that can be used to determine whether the prefetching operation specified by the operation should be aborted. The prefetch instruction may be used in conjunction with a branch predict instruction to prefetch a branch of instructions that is not predicted.

摘要翻译： 一种使用预取指令将指令预取到高速缓冲存储器中的方法。 预取指令包含目标字段，计数字段，高速缓存级别字段，刷新字段和跟踪字段。 目标字段指定预取开始的地址。 计数字段指定要预取的指令数。 flush区域表示是否应该丢弃较早的预取，并且是否中止正在进行的预取。 级别字段指定要预取指令的高速缓存的级别。 跟踪字段建立一个跟踪向量，可以用来确定该操作指定的预取操作是否应被中止。 预取指令可以与分支预测指令一起使用以预取未预测的指令分支。

公开(公告)号：US06721875B1

公开(公告)日：2004-04-13

申请号：US09510731

申请日：2000-02-22

申请人： James E McCormick, Jr. ,  Stephen R. Undy ,  Donald Charles Soltis, Jr.

发明人： James E McCormick, Jr. ,  Stephen R. Undy ,  Donald Charles Soltis, Jr.

IPC分类号： G06F1500

CPC分类号： G06F9/3853 ,  G06F9/322 ,  G06F9/324 ,  G06F9/328 ,  G06F9/3806 ,  G06F9/3844

摘要： Disclosed is a computer architecture with single-syllable IP-relative branch instructions and long IP-relative branch instructions (IP=instruction pointer). The architecture fetches instructions in multi-syllable, bundle form. Single-syllable IP-relative branch instructions occupy a single syllable in an instruction bundle, and long IP-relative branch instructions occupy two syllables in an instruction bundle. The additional syllable of the long branch carries with it additional IP-relative offset bits, which when merged with offset bits carried in a core branch syllable provide a much greater offset than is carried by a single-syllable branch alone. Thus, the long branch provides for greater reach within an address space. Use of the long branch to patch IA-64 architecture instruction bundles is also disclosed. Such a patch provides the reach of an indirect branch with the overhead of a single-syllable IP-relative branch.

摘要翻译： 公开了具有单音节IP相关分支指令和长IP相对分支指令（IP =指令指针）的计算机体系结构。 该体系结构以多音节，捆绑形式获取指令。 单音节IP相对分支指令占用指令束中的单个音节，并且长IP相对分支指令占用指令束中的两个音节。 长分支的附加音节带有附加的IP相对偏移位，当与核分支音节中携带的偏移位合并时，它提供比单音节单独承载的偏移更大的偏移。 因此，长分支在地址空间内提供更大的覆盖。 还公开了使用长分支来修补IA-64架构指令束。 这样一个补丁提供了一个间接分支的触发与单音节IP相关分支的开销。

公开(公告)号：US06711671B1

公开(公告)日：2004-03-23

申请号：US09506773

申请日：2000-02-18

申请人： Stephen R. Undy ,  Donald Charles Soltis, Jr.

发明人： Stephen R. Undy ,  Donald Charles Soltis, Jr.

IPC分类号： G06F1500

CPC分类号： G06F9/3802 ,  G06F9/3842 ,  G06F9/3861

摘要： An apparatus for and a method of ensuring that a non-speculative instruction is not fetched into an execution pipeline, where the non-speculative instruction, if fetched, may cause a cache miss that causes potentially catastrophic speculative processing, e.g., speculative transfer of data from an I/O device. When a non-speculative instruction is scheduled for a fetch into the pipeline, a translation lookaside buffer (TLB) miss is made to occur, e.g., by preventing the lowest level TLB from storing any page table entry (PTE) associated with any of the non-speculative instructions. The TLB miss prevents the occurrence of any cache miss, and causes a micro-fault to be injected into the pipeline. The micro-fault includes an address corresponding to the subject non-speculative instruction, and when it reaches the end of the pipeline, causes a redirect of instruction flow of the pipeline to the address, and thus the non-speculative instruction is fetched and executed in a non-speculative manner.

摘要翻译： 一种用于确保非推测性指令未被提取到执行流水线中的装置和方法，其中非推测性指令（如果获取）可能导致导致潜在灾难性投机处理的高速缓存未命中，例如数据的推测性传输 从I / O设备。 当调度非推测性指令以进入流水线时，会发生翻译后备缓冲区（TLB）未命中，例如，通过防止最低级TLB存储与任何一个 非投机指示。 TLB错误防止任何高速缓存未命中的发生，并导致将微故障注入到管道中。 微故障包括与主体非推测性指令对应的地址，并且当其到达流水线的末端时，导致流水线的指令流向该地址的重定向，从而取出并执行非推测性指令 以不投机的方式。

公开(公告)号：US06618801B1

公开(公告)日：2003-09-09

申请号：US09496845

申请日：2000-02-02

申请人： Patrick Knebel ,  Kevin David Safford ,  Donald Charles Soltis, Jr. ,  Joel D Lamb ,  Stephen R. Undy ,  Russell C Brockmann

发明人： Patrick Knebel ,  Kevin David Safford ,  Donald Charles Soltis, Jr. ,  Joel D Lamb ,  Stephen R. Undy ,  Russell C Brockmann

IPC分类号： G06F1500

CPC分类号： G06F9/30174 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3853

摘要： The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexor or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.

摘要翻译： 本发明是用于在单个芯片上实现两个架构的方法。 该方法使用提取引擎来检索指令。 如果指令是宏指令，则将宏指令解码为微指令，然后在仿真引擎内使用捆绑器捆绑这些微指令。 捆绑包并行发布并分发到执行引擎并包含预解码位，以便执行引擎将它们视为微指令。 在被传送到执行引擎之前，可以将指令保存在缓冲器中。 该方法还可以选择来自仿真引擎的捆绑微指令和直接来自取指引擎的本机微指令，通过使用多路复用器或其他方式。 本地微指令和捆绑的微指令都可以保存在缓冲区中。 该方法还向执行引擎发送附加信息。

公开(公告)号：US06516388B1

公开(公告)日：2003-02-04

申请号：US09662295

申请日：2000-09-15

申请人： James E. McCormick, Jr. ,  Stephen R. Undy

发明人： James E. McCormick, Jr. ,  Stephen R. Undy

IPC分类号： G06F1202

CPC分类号： G06F12/123 ,  G06F12/0862

摘要： In a cache which writes new data over less recently used data, methods and apparatus which dispense with the convention of marking new cache data as most recently used. Instead, non-referenced data is marked as less recently used when it is written into a cache, and referenced data is marked as more recently used when it is written into a cache. Referenced data may correspond to fetch data, and non-referenced data may correspond to prefetch data. Upon fetch of a data value from the cache, its use status may be updated to more recently used. The methods and apparatus have the affect of preserving (n−1)/n of a cache's entries for the storage of fetch data, while limiting the storage of prefetch data to 1/n of a cache's entries. Pollution which results from unneeded prefetch data is therefore limited to 1/n of the cache. In reality, however, pollution from unneeded prefetch data will be significantly less, as many prefetch data values will ultimately be fetched prior to their overwrite with new data, and upon their fetch, their use status can be upgraded to most recently used, thus ensuring their continued maintenance in the cache.

摘要翻译： 在通过较少使用的数据写入新数据的缓存中，不考虑最近使用的标记新的高速缓存数据的约定的方法和装置。 相反，未引用的数据在写入高速缓存时被标记为最近不被使用，并且被引用的数据被标记为在写入高速缓存时最近被使用的数据。 被引用的数据可以对应于获取数据，并且非参考数据可对应于预取数据。 从缓存中获取数据值时，其使用状态可能会更新到最近使用的状态。 这些方法和装置具有保存（n-1）/ n的缓存条目以存储获取数据的效果，同时将预取数据的存储限制到缓存的条目的1 / n。 因此，不必要的预取数据导致的污染限制在缓存的1 / n。 然而，实际上，不必要的预取数据的污染将会明显减少，因为在使用新数据覆盖之前，最终将获取许多预取数据值，并且在获取时，可以将其使用状态升级到最近使用，从而确保 他们在缓存中继续维护。

公开(公告)号：US5860096A

公开(公告)日：1999-01-12

申请号：US768417

申请日：1996-12-18

申请人： Stephen R. Undy ,  Patrick Knebel ,  Craig A. Gleason

发明人： Stephen R. Undy ,  Patrick Knebel ,  Craig A. Gleason

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3814 ,  G06F12/0897 ,  G06F9/3802

摘要： A multi-level instruction cache memory system for a computer processor. A relatively large cache has both instructions and data. The large cache is the primary source of data for the processor. A smaller cache dedicated to instructions is also provided. The smaller cache is the primary source of instructions for the processor. Instructions are copied from the larger cache to the smaller cache during times when the processor is not accessing data in the larger cache. A prefetch buffer transfers instructions from the larger cache to the smaller cache. If a cache miss occurs for the smaller cache, and the instruction is in the prefetch buffer, the system provides the instruction with no delay relative to a fetch from the smaller instruction cache. If a cache miss occurs for the smaller cache, and the instruction is being fetched from the larger cache, or available in the larger cache, the system provides the instruction with minimal delay relative to a fetch from the smaller instruction cache.

摘要翻译： 一种用于计算机处理器的多级指令高速缓冲存储器系统。 相对较大的缓存具有指令和数据。 大型缓存是处理器的主要数据源。 还提供了一个专用于指令的较小缓存。 较小的缓存是处理器的主要指令源。 在处理器未访问较大缓存中的数据的时间期间，指令将从更大的缓存复制到较小的缓存。 预取缓冲区将指令从较大的缓存传输到较小的缓存。 如果较小的缓存出现高速缓存未命中，并且该指令位于预取缓冲区中，则该系统相对于从较小的指令高速缓存提取的指令没有延迟。 如果较小的缓存出现高速缓存未命中，并且指令正在从较大的缓存中取出，或者在较大的缓存中可用，则该系统相对于从较小的指令高速缓存取出的延迟最小化。

公开(公告)号：US5829049A

公开(公告)日：1998-10-27

申请号：US785105

申请日：1997-01-21

申请人： William L. Walker ,  Mark R. Storey ,  Patrick Knebel ,  Stephen R. Undy

发明人： William L. Walker ,  Mark R. Storey ,  Patrick Knebel ,  Stephen R. Undy

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/28

CPC分类号： G06F9/30043 ,  G06F9/3853

摘要： A method of improving the performance of a computer processor by recognizing that two consecutive register instructions can be executed simultaneously and executing the two instructions simultaneously while generating a single data address and while performing exception checking on a single data address. During an instruction fetch process, two consecutive instructions are tested to determine if both are either register load instructions or register save instructions. If both instructions are load or save register instructions, the corresponding data addresses are tested to see if both data addresses are in the same double word. If both data addresses are in the same double word, then the instructions are executed simultaneously. Only one data address generation is required and exception processing is performed on only one data address. In one example embodiment, a simplified test rapidly ensures that both data addresses are in the same double word, but also requires the base addresses to be at an even word boundary. In a second embodiment, where the processor includes an alignment test as a separate test, an even more simple test rapidly ensures that both data address are in the same double word without checking alignment.

摘要翻译： 通过识别同时执行两个连续的寄存器指令并且同时执行两个指令同时生成单个数据地址并且同时对单个数据地址执行异常检查来改善计算机处理器的性能的方法。 在指令提取过程中，测试两个连续的指令，以确定两者是寄存器加载指令还是寄存器保存指令。 如果两个指令都是加载或保存寄存器指令，则对相应的数据地址进行测试，以查看两个数据地址是否都在相同的双字中。 如果两个数据地址都是相同的双字，则同时执行指令。 只需要一个数据地址生成，并且只对一个数据地址执行异常处理。 在一个示例实施例中，简化测试快速确保两个数据地址都在相同的双字中，但也要求基地址处于偶数字边界。 在第二实施例中，其中处理器包括作为单独测试的对准测试，甚至更简单的测试快速确保两个数据地址都在相同的双字中，而不检查对齐。