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11.发明申请Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权为交错多线程环境中的数字信号处理器注册文件公开(公告)号：US20060242384A1
公开(公告)日：2006-10-26
申请号：US11115916
申请日：2005-04-26
IPC分类号： G06F15/00
CPC分类号： G06F9/30149 , G06F9/3012 , G06F9/3851 , G06F9/3885
摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.
摘要翻译： 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。 处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。
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12.发明申请Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment 审中-公开用于在交错多线程环境中工作的数字信号处理器的统一非分区寄存器文件公开(公告)号：US20060230253A1
公开(公告)日：2006-10-12
申请号：US11103744
申请日：2005-04-11
IPC分类号： G06F15/00
CPC分类号： H04M1/72522 , G06F9/3012 , G06F9/3885 , H04M1/2535 , H04M2250/02
摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.
摘要翻译： 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 音序器可以支持非常长的指令字（VLIW）指令和超标量指令。 处理器装置还包括响应于定序器的第一指令执行单元，响应于定序器的第二指令执行单元，响应于定序器的第三指令执行单元，以及响应于定序器的第四指令执行单元。 此外，处理器装置包括多个寄存器文件，并且多个寄存器文件中的每一个包括多个寄存器。 多个寄存器文件耦合到定序器并耦合到第一指令执行单元，第二指令执行单元，第三指令执行单元和第四指令执行单元。
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13.发明申请公开(公告)号：US20060230257A1
公开(公告)日：2006-10-12
申请号：US11104163
申请日：2005-04-11
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3885
摘要： A processor device is disclosed and includes a memory unit and at least one interleaved multi-threading instruction pipeline. The interleaved multi-threading instruction pipeline utilizes a number of clock cycles that is less than an instruction issue rate for each of a plurality of program threads that are stored within the memory unit. The memory unit includes six instruction caches. Further, the processor device includes six register files and each of the six register files is associated with one of the six instruction caches. Each of the plurality of program threads is associated with one of the six register files. Further, each of the six program threads includes a plurality of instructions and each of the plurality of instructions is stored within one of the six instruction caches of the memory.
摘要翻译： 公开了处理器设备，并且包括存储器单元和至少一个交错多线程指令流水线。 交错多线程指令流水线利用小于存储在存储器单元内的多个程序线程中的每一个的指令发布速率的多个时钟周期。 存储单元包括六个指令高速缓存。 此外，处理器设备包括六个寄存器文件，六个寄存器文件中的每一个与六个指令高速缓存中的一个相关联。 多个程序线程中的每一个与六个寄存器文件中的一个相关联。 此外，六个程序线程中的每一个包括多个指令，并且多个指令中的每一个被存储在存储器的六个指令高速缓存之一中。
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公开(公告)号：US20060218379A1
公开(公告)日：2006-09-28
申请号：US11088607
申请日：2005-03-23
IPC分类号： G06F9/40
CPC分类号： G06F9/30149 , G06F9/3853
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encoding a plurality of instructions of a first length and a plurality of instructions of a second length. The method and system encode a header having at least one instruction length bit. The instruction bit distinguishes between instructions of the first length and instructions of the second length for an associated DSP to process in a mixed stream. The method and system distinguish between the instructions of the first length and the instructions of the second length according to the contents of the instruction length bits. The header further includes bits for distinguishing between instructions of varying lengths in an instruction packet.
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公开(公告)号：US20080091867A1
公开(公告)日：2008-04-17
申请号：US11954615
申请日：2007-12-12
IPC分类号： G06F9/26
CPC分类号： G06F9/4812 , G06F9/30123 , G06F9/3013 , G06F9/3851
摘要： A multi-threaded processor is disclosed that includes a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor. The sequencer includes an interrupt controller adapted to receive one or more interrupts and to selectively allow a first thread of the one or more threads to service at least one interrupt. The interrupt controller includes logic to preclude a second thread of the one or more threads from responding to the at least one interrupt.
摘要翻译： 公开了一种多线程处理器，其包括适于提供与多线程处理器的一个或多个线程相关联的指令的定序器。 定序器包括适于接收一个或多个中断并且选择性地允许一个或多个线程的第一线程服务于至少一个中断的中断控制器。 所述中断控制器包括排除所述一个或多个线程的第二线程以响应所述至少一个中断的逻辑。
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16.发明申请System and method of executing program threads in a multi-threaded processor 有权在多线程处理器中执行程序线程的系统和方法公开(公告)号：US20060242645A1
公开(公告)日：2006-10-26
申请号：US11115917
申请日：2005-04-26
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3853
摘要： A multithreaded processor device is disclosed and includes a first program thread and second program thread. The second program thread is execution linked to the first program thread in a lock step manner. As such, when the first program thread experiences a stall event, the second program thread is instructed to perform a no operation instruction in order to keep the second program thread execution linked to the first program thread. Also, the second program thread performs a no operation instruction during each clock cycle that the first program thread is stalled due to the stall event. When the first program thread performs a first successful operation after the stall event, the second program thread restarts normal execution.
摘要翻译： 公开了一种多线程处理器设备，并且包括第一程序线程和第二程序线程。 第二个程序线程以锁定步骤的方式执行链接到第一个程序线程。 这样，当第一程序线程经历停顿事件时，指示第二程序线程执行无操作指令，以便使第二程序线程执行与第一程序线程相关联。 此外，第二程序线程在每个时钟周期期间执行无操作指令，由于失速事件使第一程序线程停滞。 当第一程序线程在停止事件之后执行第一次成功操作时，第二程序线程重新启动正常执行。
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公开(公告)号：US20060218373A1
公开(公告)日：2006-09-28
申请号：US11089619
申请日：2005-03-24
IPC分类号： G06F9/34
CPC分类号： G06F9/35 , G06F9/3851 , G06F9/3853
摘要： A processor is operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the first register-out value and obtaining a second register-out value, and storing the second register-out value into a third register based on the program instruction. The processor is further operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the program instruction and obtaining a second register-out value, and storing the first register-out value into a third register based on the second register-out value.
摘要翻译： 处理器可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于第一寄存器输出值访问第二寄存器并获得第二寄存器值， 以及基于所述程序指令将所述第二寄存器值存储到第三寄存器中。 处理器还可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于所述程序指令访问第二寄存器并获得第二寄存器值，以及存储 基于第二寄存器值将第一寄存器值输入到第三寄存器中。
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18.发明授权Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode 失效将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法公开(公告)号：US08195916B2
公开(公告)日：2012-06-05
申请号：US12397438
申请日：2009-03-04
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/1016 , G06F2212/652 , G06F2212/654 , G06F2212/655
摘要： An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address.
摘要翻译： 公开了一种将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法。 在一个实施例中，一种方法包括基于基地址值执行第一翻译后备缓冲器（TLB）查找以检索推测性物理地址。 在基于基地址值执行TLB查找的同时，将基地址值添加到偏移值以生成有效的地址值。 该方法还包括基于可变页大小执行基地址值与有效地址值的比较，以确定推测物理地址是否对应于有效地址。
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19.发明申请Apparatus and Method to Translate Virtual Addresses to Physical Addresses in a Base Plus Offset Addressing Mode 失效在Base Plus偏移寻址模式中将虚拟地址转换为物理地址的装置和方法公开(公告)号：US20100228944A1
公开(公告)日：2010-09-09
申请号：US12397438
申请日：2009-03-04
CPC分类号： G06F12/1027 , G06F2212/1016 , G06F2212/652 , G06F2212/654 , G06F2212/655
摘要： An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address.
摘要翻译： 公开了一种将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法。 在一个实施例中，一种方法包括基于基地址值执行第一翻译后备缓冲器（TLB）查找以检索推测性物理地址。 在基于基地址值执行TLB查找的同时，将基地址值添加到偏移值以生成有效的地址值。 该方法还包括基于可变页大小执行基地址值与有效地址值的比较，以确定推测物理地址是否对应于有效地址。
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20.发明授权Method and system to indicate an exception-triggering page within a microprocessor 有权用于指示微处理器内的异常触发页面的方法和系统公开(公告)号：US07689806B2
公开(公告)日：2010-03-30
申请号：US11487284
申请日：2006-07-14
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/684
摘要： A method and system to indicate which page within a software-managed page table triggers an exception within a microprocessor, such as, for example, a digital signal processor, wherein a software-managed translation lookaside buffer (TLB) module receives a virtual address produced by an instruction within a Very Long Instruction Word (VLIW) packet, such as, for example, a fetch instruction, and further compares the virtual address to each stored TLB entry. If a match exists, then the TLB module outputs a corresponding mapped physical address for the instruction. Otherwise, if the VLIW packet spans two pages, where a first page is present as a TLB entry within the TLB module and the second page is missing from the stored TLB entries, an indication bit within a data field of a control register is set to identify the TLB miss exception to a software management unit. The software management unit retrieves the indication bit information from the register and further performs a page table look-up within the software-managed page table using the indication bit information in order to retrieve the missing page information. Subsequently, the missing page information is written into a new TLB entry within the TLB module for subsequent virtual address translation and execution of the packet of instructions.
摘要翻译： 一种方法和系统，用于指示软件管理的页表内的哪个页面在微处理器（例如数字信号处理器）内触发异常，其中软件管理的翻译后备缓冲器（TLB）模块接收产生的虚拟地址 通过超长指令字（VLIW）分组（例如，取指令）中的指令，并且还将虚拟地址与每个存储的TLB条目进行比较。 如果匹配存在，则TLB模块输出相应的映射物理地址。 否则，如果VLIW分组跨越两页，其中第一页作为TLB模块中的TLB条目存在，并且第二页从存储的TLB条目丢失，则将控制寄存器的数据字段内的指示位设置为 识别软件管理单元的TLB错误异常。 软件管理单元从寄存器检索指示位信息，并使用指示位信息进一步在软件管理的页表中执行页表查找，以便检索丢失页信息。 随后，丢失的页面信息被写入TLB模块中的新TLB条目，用于随后的虚拟地址转换和指令分组的执行。
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