Method For Production Of Micro-Optics Structures
    12.
    发明申请
    Method For Production Of Micro-Optics Structures 审中-公开
    微光学结构的生产方法

    公开(公告)号:US20070218372A1

    公开(公告)日:2007-09-20

    申请号:US10565623

    申请日:2004-07-25

    IPC分类号: G03F1/00 G02B26/00

    摘要: A novel method for fabricating a micro-optics structure, having at least one lenslet array, is presented. A writing mask is provided being configured in accordance with an arrangement of the lenslet array to be manufactured. The writing mask is applied to a structure formed by a photosensitive layer of a predetermined thickness carried by a substrate, and the photosensitive layer is exposed through the writing mask using a predetermined spectral range of the exposure and a predetermined distance between the mask and said photosensitive layer, to thereby pattern the photosensitive layer through a diffractive optical element of said mask. The so-obtained pattern is in the form of optical nonhomogeneities in the photosensitive layer material, defining the lenslet array within the photosensitive layer.

    摘要翻译: 提出了一种用于制造具有至少一个小透镜阵列的微光学结构的新颖方法。 根据要制造的小透镜阵列的布置来配置书写掩模。 写入掩模应用于由基板承载的预定厚度的感光层形成的结构,并且通过曝光的预定光谱范围通过写入掩模曝光感光层,并且掩模和所述感光层之间的预定距离 从而通过所述掩模的衍射光学元件对感光层进行图案化。 如此获得的图案是感光层材料中的光学不均匀性的形式,在感光层内限定了小透镜阵列。

    Enhancing processing efficiency in large instruction width processors
    13.
    发明申请
    Enhancing processing efficiency in large instruction width processors 有权
    提高大指令宽度处理器的处理效率

    公开(公告)号:US20100180102A1

    公开(公告)日:2010-07-15

    申请号:US12354034

    申请日:2009-01-15

    IPC分类号: G06F9/38

    摘要: A processor includes one or more processing units, an execution pipeline and control circuitry. The execution pipeline includes at least first and second pipeline stages that are cascaded so that program instructions, specifying operations to be performed by the processing units in successive cycles of the pipeline, are fetched from a memory by the first pipeline stage and conveyed to the second pipeline stage, which causes the processing units to perform the specified operations.The control circuitry is coupled, upon determining that a program instruction that is present in the second pipeline stage in a first cycle of the pipeline is to be executed again in a subsequent cycle of the pipeline, to cause the execution pipeline to reuse the program instruction in one of the pipeline stages without re-fetching the program instruction from the memory.

    摘要翻译: 处理器包括一个或多个处理单元,执行流水线和控制电路。 执行流水线至少包括第一和第二流水线级级,以使得在流水线的连续循环中由处理单元执行的指定操作的程序指令由第一流水线级从存储器中提取并被传送到第二流水线级 流水线阶段,使处理单元执行指定的操作。 控制电路在确定将在流水线的后续周期中再次执行在流水线的第一周期中存在于第二流水线阶段中的程序指令以使得执行流水线重用程序指令时被耦合 在一个流水线阶段,而不用从存储器中重新获得程序指令。

    Enhancing processing efficiency in large instruction width processors
    14.
    发明授权
    Enhancing processing efficiency in large instruction width processors 有权
    提高大指令宽度处理器的处理效率

    公开(公告)号:US09170816B2

    公开(公告)日:2015-10-27

    申请号:US12354034

    申请日:2009-01-15

    摘要: A processor includes one or more processing units, an execution pipeline and control circuitry. The execution pipeline includes at least first and second pipeline stages that are cascaded so that program instructions, specifying operations to be performed by the processing units in successive cycles of the pipeline, are fetched from a memory by the first pipeline stage and conveyed to the second pipeline stage, which causes the processing units to perform the specified operations. The control circuitry is coupled, upon determining that a program instruction that is present in the second pipeline stage in a first cycle of the pipeline is to be executed again in a subsequent cycle of the pipeline, to cause the execution pipeline to reuse the program instruction in one of the pipeline stages without re-fetching the program instruction from the memory.

    摘要翻译: 处理器包括一个或多个处理单元,执行流水线和控制电路。 执行流水线至少包括第一和第二流水线级级,以使得在流水线的连续循环中由处理单元执行的指定操作的程序指令由第一流水线级从存储器中提取并被传送到第二流水线级 流水线阶段,使处理单元执行指定的操作。 控制电路在确定将在流水线的后续周期中再次执行在流水线的第一周期中存在于第二流水线阶段中的程序指令以使得执行流水线重用程序指令时被耦合 在一个流水线阶段,而不用从存储器中重新获得程序指令。

    VLSI Circuit Verification
    15.
    发明申请
    VLSI Circuit Verification 审中-公开
    VLSI电路验证

    公开(公告)号:US20140088911A1

    公开(公告)日:2014-03-27

    申请号:US14116776

    申请日:2012-05-24

    IPC分类号: G01R31/28

    摘要: A method of connecting to an integrated circuit. A target integrated circuit (102) is provided with an embedded agent (104) for exporting signals. While the target integrated circuit (102) is operating, data signals from one or more collection points (252) in the integrated circuit (102) are collected by the embedded agent (104), at least at a clock rate of operation of the integrated circuit at the one or more collection points (252), in parallel to the target circuit (102) operation. The collected data signals are inserted into packets, by the embedded agent (104) and the packets are transmitted to a unit external to the integrated circuit, in real time.

    摘要翻译: 一种连接到集成电路的方法。 目标集成电路(102)设置有用于输出信号的嵌入式代理(104)。 当目标集成电路(102)工作时,来自集成电路(102)中的一个或多个收集点(252)的数据信号由嵌入式代理(104)收集,至少以集成的 在一个或多个收集点(252)处与目标电路(102)操作并联的电路。 所收集的数据信号由嵌入式代理(104)插入到分组中,并且分组被实时传输到集成电路外部的单元。

    Projection system and method
    16.
    发明申请
    Projection system and method 审中-公开
    投影系统和方法

    公开(公告)号:US20060279662A1

    公开(公告)日:2006-12-14

    申请号:US10549173

    申请日:2004-03-16

    IPC分类号: H04N9/31

    摘要: An image projection system and method are presented to project an image on at least one of first and second projection planes. The system comprises a light source system including one or more light source assemblies operable to generate light of one or more predetermined wavelength range; a spatial light modulator (SLM) system including one or more SLM units operable to spatially modulate input light in accordance with an image to be directly projected or viewed; and two optical assemblies associated with two spatially separated light propagation channels, respectively, to direct light to, respectively, the first and second projection planes with desired image magnification. The system is configured to selectively direct the input light propagating towards the SLM system or light modulated by the SLM system to propagate along at least one of the two channels associated with the first and second projection planes, respectively.

    摘要翻译: 呈现图像投影系统和方法以在第一和第二投影平面中的至少一个上投影图像。 该系统包括光源系统,该光源系统包括可操作以产生一个或多个预定波长范围的光的一个或多个光源组件; 包括一个或多个SLM单元的空间光调制器(SLM)系统,其可操作以根据直接投影或观看的图像对输入光进行空间调制; 以及分别与两个空间分离的光传播通道相关联的两个光学组件,以分别以所需的图像放大率将光引导到第一和第二投影平面。 该系统被配置为选择性地引导朝向SLM系统传播的输入光或由SLM系统调制的光分别沿与第一和第二投影平面相关联的两个通道中的至少一个传播。

    Fast all-optical switches and attenuators
    17.
    发明申请
    Fast all-optical switches and attenuators 审中-公开
    快速全光开关和衰减器

    公开(公告)号:US20050174639A1

    公开(公告)日:2005-08-11

    申请号:US10470177

    申请日:2002-01-22

    摘要: A polarizing beam-splitter apparatus, comprising: an input port through which an input beam of lights is provided; a first polarizing beam splitter that receives the input beam and splits the beam into at least a first and second beam, said first beam having substantially a first desired polarization state and said second beam having a second polarization state orthogonal to said first polarization state but possibly admixed with the first polarization state; and an optical system that receives the second beam and provides a third beam having the second polarization state and a smaller admixture of the second polarization state than the second beam.

    摘要翻译: 一种偏振分束器装置,包括:输入端口,通过所述输入端口提供输入光束; 第一偏振分束器,其接收所述输入光束并且将所述光束分解成至少第一和第二光束,所述第一光束具有基本上第一期望的偏振状态,并且所述第二光束具有与所述第一偏振状态正交的第二偏振态,但是可能 与第一极化状态混合; 以及光学系统,其接收第二光束并提供具有第二偏振状态的第三光束和比第二光束更小的第二偏振态的混合物。