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27 条记录 (耗时 0.028 秒)

    Startup/yank circuit for self-biased phase-locked loops
    12.
    发明申请
    Startup/yank circuit for self-biased phase-locked loops 有权
    启动/匝电路用于自偏置锁相环

    公开(公告)号：US20060244542A1

    公开(公告)日：2006-11-02

    申请号：US11476690

    申请日：2006-06-29

    申请人： Ernest Knoll ,  Eyal Fayneh

    发明人： Ernest Knoll ,  Eyal Fayneh

    IPC分类号： H03L7/00

    CPC分类号： H03L7/10 ,  H03L7/0893 ,  H03L7/12 ,  H03L7/18

    摘要： An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

    摘要翻译： 用于控制锁相环的装置包括用于检测启动条件和绞盘状况中的至少一个的检测器和用于控制电荷泵和锁相环之间的电流的控制器。 如果检测到启动条件，则控制器从连接到锁相环的环路滤波器的控制节点吸收电流。 这反过来导致偏置电压增加，直到锁相环从启动模式转换到正常采集模式。 电流吸收器由虚拟电荷泵提供，并且通过检测PLL禁止状态的结束来确定启动条件。 如果检测到牦牛病情，则连接到锁相环的相位频率检测器的电荷泵控制偏置电压，直到反馈频率变得低于参考频率。 在两种操作模式下控制锁相环的方法可以使用上述装置。

    High-accuracy continuous duty-cycle correction circuit
    13.
    发明授权
    High-accuracy continuous duty-cycle correction circuit 有权
    高精度连续工作周期校正电路

    公开(公告)号：US07120839B2

    公开(公告)日：2006-10-10

    申请号：US10645660

    申请日：2003-08-22

    申请人： Eyal Fayneh ,  Ernest Knoll

    发明人： Eyal Fayneh ,  Ernest Knoll

    IPC分类号： G11B20/22 ,  G11B20/24

    CPC分类号： G06F1/04 ,  H03K5/1565

    摘要： A control circuit corrects duty-cycle distortion of clock signals accurately and with a fast and continuous response over a wide dynamic range. In one embodiment, the duty-cycle correction circuit includes a self-biased loop that corrects duty-cycle distortions to preferably less than +/−1%. The duty-cycle correction circuit also compensates for changes in a supply voltage. These corrections may take place on a continuous basis, not only during a testing period but also during normal operation of the host system driven by the clock signals.

    摘要翻译： 控制电路在宽动态范围内精确地和快速连续的响应来校正时钟信号的占空比失真。 在一个实施例中，占空比校正电路包括将占空比失真校正至优选小于+/- 1％的自偏置环路。 占空比校正电路还补偿电源电压的变化。 不仅在测试期间，而且在由时钟信号驱动的主机系统的正常操作期间，这些校正可以连续进行。

    Adaptive integrated PLL loop filter
    14.
    发明授权
    Adaptive integrated PLL loop filter 有权
    自适应集成PLL环路滤波器

    公开(公告)号：US06546059B1

    公开(公告)日：2003-04-08

    申请号：US09473585

    申请日：1999-12-28

    申请人： Ernest Knoll ,  Eyal Fayneh

    发明人： Ernest Knoll ,  Eyal Fayneh

    IPC分类号： H04L2549

    CPC分类号： H03L7/0893 ,  H03L7/093

    摘要： A loop filter in the phase-locked loop includes a capacitor having a specific capacitance value. The loop filter also includes an amplifier coupled to a node of the capacitor. The amplifier amplifies a signal at the node in a way that increases the equivalent capacitance value without physically changing the capacitor.

    摘要翻译： 锁相环中的环路滤波器包括具有特定电容值的电容器。 环路滤波器还包括耦合到电容器的节点的放大器。 放大器以增加等效电容值的方式放大节点处的信号，而不会物理改变电容器。

    Yank detection circuit for self-biased phase locked loops
    17.
    发明授权
    Yank detection circuit for self-biased phase locked loops 有权
    用于自偏置锁相环的Yank检测电路

    公开(公告)号：US07095289B2

    公开(公告)日：2006-08-22

    申请号：US11122064

    申请日：2005-05-05

    申请人： Ernest Knoll ,  Eyal Fayneh

    发明人： Ernest Knoll ,  Eyal Fayneh

    IPC分类号： G01R23/12 ,  H03L7/00 ,  H03L7/099 ,  H03L7/06

    CPC分类号： H03L7/10 ,  H03L7/0893 ,  H03L7/12 ,  H03L7/18

    摘要： An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

    摘要翻译： 用于控制锁相环的装置包括用于检测启动条件和绞盘状况中的至少一个的检测器和用于控制电荷泵和锁相环之间的电流的控制器。 如果检测到启动条件，则控制器从连接到锁相环的环路滤波器的控制节点吸收电流。 这反过来导致偏置电压增加，直到锁相环从启动模式转换到正常采集模式。 电流吸收器由虚拟电荷泵提供，并且通过检测PLL禁止状态的结束来确定启动条件。 如果检测到牦牛病情，则连接到锁相环的相位频率检测器的电荷泵控制偏置电压，直到反馈频率变得低于参考频率。 在两种操作模式下控制锁相环的方法可以使用上述装置。

    Method for clock generator lock-time reduction during speedstep transition
    18.
    发明授权
    Method for clock generator lock-time reduction during speedstep transition 失效
    在速度转换过程中时钟发生器锁定时间减少的方法

    公开(公告)号：US06914490B2

    公开(公告)日：2005-07-05

    申请号：US10446724

    申请日：2003-05-29

    申请人： Eyal Fayneh ,  Ernest Knoll

    发明人： Eyal Fayneh ,  Ernest Knoll

    IPC分类号： H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03L7/00

    CPC分类号： H03L7/107 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1072

    摘要： A method for controlling a phase-locked loop includes receiving a frequency change signal and electrically isolating a VCO control node of the phase-locked loop from at least one charge pump of the loop. During this isolation period, the VCO control node voltage is held at a constant value equal to the voltage that existed before the frequency change signal was received. One or more parameters of the PLL are then altered in a manner that will ensure generation of a newly desired output frequency. These parameters include but are not limited to a feedback divider value and a reference frequency input into the PLL. The new output frequency may be above or below the pre-change signal frequency depending, for example, on a mode of operation of a host system. When the VCO control node is once again electrically connected to the charge pump, the PLL locks on to the desired output frequency. Through this method, frequency change is accomplished without performing a startup process and the time to perform a frequency acquisition process is significantly reduced.

    摘要翻译： 用于控制锁相环的方法包括接收频率变化信号并将锁相环的VCO控制节点与环路的至少一个电荷泵电隔离。 在该隔离期间，VCO控制节点电压保持在等于接收到频率变化信号之前存在的电压的恒定值。 PLL的一个或多个参数然后以将确保新产生期望的输出频率的方式改变。 这些参数包括但不限于输入到PLL中的反馈分频器值和参考频率。 新的输出频率可以高于或低于预先改变的信号频率，这取决于例如主机系统的操作模式。 当VCO控制节点再次电连接到电荷泵时，PLL锁定到期望的输出频率。 通过这种方法，在不执行启动过程的情况下实现频率改变，并且显着地减少执行频率获取过程的时间。

    On-chip filter-regulator for a microprocessor phase locked loop supply
    20.
    发明授权
    On-chip filter-regulator for a microprocessor phase locked loop supply 有权
    用于微处理器锁相环电路的片上滤波调节器

    公开(公告)号：US06313615B1

    公开(公告)日：2001-11-06

    申请号：US09661138

    申请日：2000-09-13

    申请人： Eyal Fayneh ,  Ernest Knoll

    发明人： Eyal Fayneh ,  Ernest Knoll

    IPC分类号： G05F156

    CPC分类号： G05F1/575 ,  H03L7/06

    摘要： An on-chip, e.g., on a microprocessor, super filter-regulator acts as a voltage regulator and a low-pass filter. The voltage regulator generates a constant DC output voltage and regulates the DC voltage against instantaneous load changes. The low-pass filter and actively filters AC interference out of the DC output voltage. The super filter-regulator provides the filtered and regulated DC voltage to a phase locked loop circuit.

    摘要翻译： 片上，例如在微处理器上，超滤器调节器用作电压调节器和低通滤波器。 电压调节器产生恒定的直流输出电压，并根据瞬时负载变化调节直流电压。 低通滤波器主动滤除直流输出电压的交流干扰。 超级滤波器调节器将滤波和调节的直流电压提供给锁相环电路。