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公开(公告)号:US07564299B2
公开(公告)日:2009-07-21
申请号:US11210050
申请日:2005-08-22
申请人: Joseph Shor , Eyal Fayneh
发明人: Joseph Shor , Eyal Fayneh
CPC分类号: G05F1/565
摘要: In some embodiments, regulator circuits are provided.
摘要翻译: 在一些实施例中,提供了调节器电路。
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公开(公告)号:US20070040603A1
公开(公告)日:2007-02-22
申请号:US11210050
申请日:2005-08-22
申请人: Joseph Shor , Eyal Fayneh
发明人: Joseph Shor , Eyal Fayneh
IPC分类号: G05F1/10
CPC分类号: G05F1/565
摘要: In some embodiments, regulator circuits are provided.
摘要翻译: 在一些实施例中,提供了调节器电路。
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公开(公告)号:US07605668B2
公开(公告)日:2009-10-20
申请号:US11609819
申请日:2006-12-12
申请人: Eyal Fayneh , Ernest Knoll
发明人: Eyal Fayneh , Ernest Knoll
IPC分类号: H03B5/24
CPC分类号: H03B5/20 , H03K3/0315 , H03K5/133 , H03K2005/00045 , H03K2005/00071 , H03L7/0995
摘要: Disclosed herein are embodiments of controllably variable capacitor loads that may be used with delay stages or other elements, for example, in a voltage controlled oscillator.
摘要翻译: 这里公开的可控可变电容器负载的实施例可以与延迟级或其他元件一起使用,例如在压控振荡器中。
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公开(公告)号:US20070233444A1
公开(公告)日:2007-10-04
申请号:US11395537
申请日:2006-03-31
申请人: Frank O'Mahony , Haydar Kutuk , Bryan Casper , Eyal Fayneh , Sivakumar Mudanai , Wei-kai Shih , Farag Fattouh
发明人: Frank O'Mahony , Haydar Kutuk , Bryan Casper , Eyal Fayneh , Sivakumar Mudanai , Wei-kai Shih , Farag Fattouh
IPC分类号: G06F17/50
CPC分类号: G06F17/5036
摘要: In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.
摘要翻译: 通常,在一个方面,本公开描述了一种用于在时域电路仿真中模拟各种类型的器件噪声的模拟器。 模拟器能够为晶体管以及无源元件(如电阻)增加噪声。 模拟器使用与设备并联的至少一个电流源来模拟噪声。 电流源产生随机电流输出以根据随机高斯数和器件噪声的标准偏差来模拟器件噪声。 可以基于在该模拟时间和更新时间具有特定偏压的装置的噪声功率谱密度来确定噪声标准偏差。 模拟器能够通过利用具有不同更新步骤的多个电流源来模拟具有恒定或单调降低的噪声频谱(例如,热噪声,闪烁噪声)的任何噪声源。 模拟器与标准电路模拟器兼容。
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公开(公告)号:US07265637B2
公开(公告)日:2007-09-04
申请号:US11476690
申请日:2006-06-29
申请人: Ernest Knoll , Eyal Fayneh
发明人: Ernest Knoll , Eyal Fayneh
IPC分类号: H03L7/00
CPC分类号: H03L7/10 , H03L7/0893 , H03L7/12 , H03L7/18
摘要: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.
摘要翻译: 用于控制锁相环的装置包括用于检测启动条件和绞盘状况中的至少一个的检测器和用于控制电荷泵和锁相环之间的电流的控制器。 如果检测到启动条件,则控制器从连接到锁相环的环路滤波器的控制节点吸收电流。 这反过来导致偏置电压增加,直到锁相环从启动模式转换到正常采集模式。 电流吸收器由虚拟电荷泵提供,并且通过检测PLL禁止状态的结束来确定启动条件。 如果检测到牦牛病情,则连接到锁相环的相位频率检测器的电荷泵控制偏置电压,直到反馈频率变得低于参考频率。 在两种操作模式下控制锁相环的方法可以使用上述装置。
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公开(公告)号:US20080150596A1
公开(公告)日:2008-06-26
申请号:US11615753
申请日:2006-12-22
申请人: Eyal Fayneh , Ernest Knoll
发明人: Eyal Fayneh , Ernest Knoll
IPC分类号: H03L7/06
CPC分类号: H03L7/0896 , H03L2207/06
摘要: Disclosed herein are embodiments of a charge pump that can provide an output voltage with an output current that remains sufficiently constant over an operating range of the output voltage
摘要翻译: 这里公开的电荷泵的实施例可以提供输出电压,输出电流在输出电压的工作范围内保持足够恒定
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公开(公告)号:US20050206459A1
公开(公告)日:2005-09-22
申请号:US11122064
申请日:2005-05-05
申请人: Ernest Knoll , Eyal Fayneh
发明人: Ernest Knoll , Eyal Fayneh
CPC分类号: H03L7/10 , H03L7/0893 , H03L7/12 , H03L7/18
摘要: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.
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公开(公告)号:US06894569B2
公开(公告)日:2005-05-17
申请号:US10330556
申请日:2002-12-30
申请人: Eyal Fayneh , Ernest Knoll
发明人: Eyal Fayneh , Ernest Knoll
CPC分类号: H03L7/0893 , H03L7/0896 , H03L7/18
摘要: A charge pump includes a charge circuit switch, a pump circuit switch, and a controller for generating a first control signal for switching the charge circuit switch and a second control signal for switching the pump circuit. In order to reduce the effects of self-jitter and improve signal quality, the controller generates the first and second control signals so that they have a same amplitude and slew rate. This results in improving steady-state phase error (DC skew). To further improve performance, current sources of the charge pump are controlled to operate continuously. This advantageously minimizes parastic switching currents. The charge pump may be incorporated within a phase-locked loop for purposes of generating frequency signals. The phase-locked loop may be self-biased. A processing system having, for example, a microprocessor-based computing architecture may advantageously include the phase-locked loop for performing any one of a variety of applications.
摘要翻译: 电荷泵包括充电电路开关,泵电路开关和用于产生用于切换充电电路开关的第一控制信号的控制器和用于切换泵电路的第二控制信号。 为了减少自抖动的影响并提高信号质量,控制器产生第一和第二控制信号,使它们具有相同的幅度和转换速率。 这导致稳态相位误差(DC偏移)的改善。 为了进一步提高性能,电流泵的电流源被控制以连续工作。 这有利地最小化了临时开关电流。 为了产生频率信号的目的,电荷泵可以结合在锁相环内。 锁相环可以是自偏置的。 具有例如基于微处理器的计算架构的处理系统可以有利地包括用于执行各种应用中的任何一个的锁相环。
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公开(公告)号:US06630855B2
公开(公告)日:2003-10-07
申请号:US09819716
申请日:2001-03-29
申请人: Eyal Fayneh , Ernest Knol
发明人: Eyal Fayneh , Ernest Knol
IPC分类号: H03K512
CPC分类号: G06F1/10
摘要: A phase alignment technique includes providing a clock signal to a first clock distribution spine and providing at least one additional clock distribution spine. One PLL (Phase Locked Loop) is provided for each additional clock distribution spine, each PLL having an REF input and an FBK input and an output. The REF input of each PLL is connected to the first clock distribution spine and the FBK input of each PLL is connected to its respective clock distribution spine and the output of each PLL is connected to its respective clock distribution spine to provide a clock signal thereto. Each PLL provides phase alignment between the clock signal on the first clock distribution spine and the clock signal outputted by the PLL to its respective clock distribution spine. The first clock distribution spine and each additional clock distribution spine and its respective PLL may be disposed on an integrated circuit die.
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公开(公告)号:US20140006808A1
公开(公告)日:2014-01-02
申请号:US13538262
申请日:2012-06-29
申请人: Gregory Sizikov , Michael Zelikson , Efraim Rotem , Eyal Fayneh
发明人: Gregory Sizikov , Michael Zelikson , Efraim Rotem , Eyal Fayneh
摘要: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
摘要翻译: 这里描述的集成电路包括:具有一个或多个桥式驱动器的开关电压调节器(SVR),以向多个电源域提供稳定的电源; 以及功率控制单元(PCU),其可操作以根据所述多个功率域的状态来调整所述SVR的开关频率,其中所述一个或多个桥接驱动器的驱动强度或有源相位计数也由所述SVR的逻辑单元 当SVR的开关频率被调整时。
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