公开(公告)号：US07075336B2

公开(公告)日：2006-07-11

申请号：US10184425

申请日：2002-06-28

申请人： Naohito Kojima ,  Fumihiro Minami ,  Masami Murakata ,  Takashi Ishioka

发明人： Naohito Kojima ,  Fumihiro Minami ,  Masami Murakata ,  Takashi Ishioka

IPC分类号： H03K19/00 ,  H03K19/096 ,  G06F9/45 ,  G06F17/50 ,  G06F1/12

CPC分类号： G06F17/5045 ,  G06F1/10

摘要： A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.

公开(公告)号：US06967288B2

公开(公告)日：2005-11-22

申请号：US10110677

申请日：2001-08-17

申请人： Takashi Ohsawa ,  Fumihiro Minami ,  Mutsuo Sekiya

发明人： Takashi Ohsawa ,  Fumihiro Minami ,  Mutsuo Sekiya

IPC分类号： F21S8/10 ,  F21V19/00 ,  F21V25/00 ,  H01B9/02 ,  H01R9/03 ,  H02G3/00 ,  H01B17/22

CPC分类号： H01R9/032 ,  B60Q1/0088 ,  B60Q1/0094 ,  F21S41/17 ,  F21S41/192 ,  F21V25/00 ,  F21W2107/10 ,  H01B9/028 ,  H01R24/562 ,  H01R2107/00

摘要： A shielding wire is provided with a first conductor, a shield for sheathing the first conductor through an insulating member, and a second conductor which is in contact with the shield. Therefore, a troublesome step of unknitting the braid of the shield is eliminated, and the work is done at a higher efficiency and the manufacturing cost is reduced.

摘要翻译： 屏蔽线设置有第一导体，用于通过绝缘构件覆盖第一导体的屏蔽件和与屏蔽件接触的第二导体。 因此，消除了屏蔽编织物的打结的麻烦的步骤，工作以更高的效率进行，制造成本降低。

公开(公告)号：US06867673B2

公开(公告)日：2005-03-15

申请号：US10110689

申请日：2001-08-17

申请人： Fumihiro Minami ,  Mutsuo Sekiya ,  Masaru Kibi

发明人： Fumihiro Minami ,  Mutsuo Sekiya ,  Masaru Kibi

IPC分类号： F21Y101/00 ,  H01F5/04 ,  H01F27/02 ,  H01F27/26 ,  H01F27/28 ,  H01F38/10 ,  H05B41/04 ,  H01F27/04

CPC分类号： H05B41/042 ,  H01F5/04 ,  H01F27/022 ,  H01F27/266 ,  H01F27/2828 ,  H01F38/10

摘要： Providing a high-voltage-side terminal with means for preventing a core inserted into a central hole of a bobbin from getting out of position securely fixes the core to the predetermined position, at the time a transformer which is a part of an ignitor is assembled, during the work proceeds from the inserting step of the core to the next step. Thus, at the time the ignitor-integral type bulb socket is assembled, the core hardly moves out of the predetermined position and there is a less possibility that the core gets out of position. Accordingly, this does not require so high machining accuracy of both members and reduces the cost for machining the product as well as for inspecting the dimension control or the like.

摘要翻译： 提供具有用于防止插入到线轴的中心孔中的铁芯脱离位置的装置的高压端子将芯件牢固地固定到预定位置，在作为点火器的一部分的变压器被组装时 在工作期间从核心的插入步骤进行到下一步骤。 因此，在点火器整体式灯泡插座组装时，芯部几乎不会移动到预定位置之外，并且芯体脱离位置的可能性较小。 因此，这不需要两个部件的高加工精度，并且降低了加工产品的成本以及检查尺寸控制等。

公开(公告)号：US20110280035A1

公开(公告)日：2011-11-17

申请号：US13144852

申请日：2009-11-04

申请人： Fumihiro Minami ,  Takashi Ohsawa

发明人： Fumihiro Minami ,  Takashi Ohsawa

IPC分类号： B60Q1/04

CPC分类号： B60Q1/0094 ,  F21S41/17 ,  F21S41/192

摘要： A lighting device for a headlamp light source includes an connector to be connected to cables for supplying power to the light source, and attached to the bottom of a headlamp case that houses a light source, wherein the output connector is formed such that when the lighting device is attached to the headlamp case, the bottom of a connection opening to which cables of the output connector are connected is disposed at a higher position than a bottom face inside the headlamp case.

摘要翻译： 一种用于前照灯光源的照明装置，包括：连接器，用于向光源提供电力的电缆，并连接到容纳光源的头灯箱的底部，其中，所述输出连接器形成为当照明 装置附接到前照灯外壳，连接到输出连接器的电缆的连接开口的底部设置在比前照灯外壳内的底面更高的位置。

公开(公告)号：US07211737B2

公开(公告)日：2007-05-01

申请号：US10110678

申请日：2001-08-17

申请人： Fumihiro Minami ,  Yukari Yamasaki ,  Mutsuo Sekiya

发明人： Fumihiro Minami ,  Yukari Yamasaki ,  Mutsuo Sekiya

IPC分类号： H01R12/04 ,  H05K1/16

CPC分类号： H01R33/9456 ,  H01R33/7635 ,  H01R33/7685 ,  H01R33/9756 ,  H01R2201/08 ,  H01R2201/26 ,  H05K3/301 ,  Y10T29/49144

摘要： A mounting board has a board, retaining members mounted on the upper surface of the board, and a part retained by the retaining members. The part is mounted such that at least a part thereof is arranged below the lower surface of the board, and that the part is electrically connected to the board through the retaining members. Such an arrangement as described above eliminates the need of connecting the discharge gap element to the board by using lead wires, and of mounting it on the upper surface of the board. This lowers the height of the board and admits an elevated part.

摘要翻译： 安装板具有板，安装在板的上表面上的保持构件和由保持构件保持的部分。 该部件被安装成使得其至少一部分布置在板的下表面下方，并且该部件通过保持构件与板电连接。 如上所述的这种布置消除了通过使用引线将放电间隙元件连接到电路板并将其安装在电路板的上表面上的需要。 这降低了板的高度，并承认升高的部分。

公开(公告)号：US20060184908A1

公开(公告)日：2006-08-17

申请号：US11347771

申请日：2006-02-03

申请人： Fumihiro Minami ,  Toshiya Kotani

发明人： Fumihiro Minami ,  Toshiya Kotani

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： A method for generating layout data of a semiconductor integrated circuit includes applying optical proximity correction conditions to cells so as to generate cell patterns, selecting cell patterns to correspond cells, based on layout information of cells along a specified signal propagating path; calculating delay times for the signal propagating path for combinations of cell patterns; selecting a combination of cell patterns, based on lengths of the calculated delay times and the allowable delay time; and generating layout data of the signal propagating path using the selected combination.

摘要翻译： 一种用于生成半导体集成电路的布局数据的方法包括：对单元施加光学邻近校正条件，以便根据指定的信号传播路径的单元的布局信息产生单元格图形，选择对应单元格的单元图案; 计算用于信元模式组合的信号传播路径的延迟时间; 基于计算的延迟时间的长度和允许的延迟时间来选择单元格图案的组合; 以及使用所选择的组合生成信号传播路径的布局数据。

公开(公告)号：US20050017653A1

公开(公告)日：2005-01-27

申请号：US10895336

申请日：2004-07-21

申请人： Fumihiro Minami ,  Takashi Ohsawa ,  Kinsho Ando

发明人： Fumihiro Minami ,  Takashi Ohsawa ,  Kinsho Ando

IPC分类号： F21V23/02 ,  F21S8/10 ,  F21V23/00 ,  H05B41/04 ,  G05F1/00

CPC分类号： H05B41/042

摘要： A through hole that is slightly larger than a size of a rear end of a transformer container is formed in a rear cover constituting a part of an external wall of a starting circuit unit. The transformer container houses therein a transformer and constitutes a transformer portion. The transformer portion is assembled such that a rear end of the transformer container projects from the through hole. This allows the transformer container to constitute a part of the external wall of the starting circuit unit.

摘要翻译： 在构成起动电路单元的外壁的一部分的后盖中形成稍大于变压器容器的后端的尺寸的通孔。 变压器容器内装有变压器并构成变压器部分。 变压器部分被组装成使得变压器容器的后端从通孔突出。 这允许变压器容器构成起动电路单元的外壁的一部分。

公开(公告)号：US06388380B1

公开(公告)日：2002-05-14

申请号：US09721960

申请日：2000-11-27

申请人： Fumihiro Minami ,  Takashi Ohsawa

发明人： Fumihiro Minami ,  Takashi Ohsawa

IPC分类号： H01J744

CPC分类号： H05B41/042

摘要： An electric discharge lamp lighting device wherein a high voltage generating transformer 10 comprises a secondary coil 13 wound on an outer side of a laminated core 12 disposed in the center of a bobbin 11 and a primary coil 14 wound on an outer side of said secondary coil 13. A high voltage output terminal 13a of said secondary coil 13 is connected to a high voltage terminal of an HID lamp through a terminal 12a of a laminated core 12. A low voltage input terminal 13b of said secondary coil 13 is connected to a primary coil 14. As a result, insulation volume can be reduced and a reduction in the size of the device can be achieved.

摘要翻译： 一种放电灯点亮装置，其中高压发生变压器10包括缠绕在设置在线轴11的中心的层叠铁芯12的外侧的次级线圈13和缠绕在所述次级线圈的外侧的初级线圈14 所述次级线圈13的高电压输出端子13a通过叠层铁芯12的端子12a与HID灯的高电压端子连接。所述次级线圈13的低电压输入端子13b与主电路 结果，可以减小绝缘体积并且可以实现器件尺寸的减小。

公开(公告)号：US6110222A

公开(公告)日：2000-08-29

申请号：US76490

申请日：1998-05-13

申请人： Fumihiro Minami ,  Masako Murofushi

发明人： Fumihiro Minami ,  Masako Murofushi

IPC分类号： H01L21/82 ,  G06F17/50

CPC分类号： G06F17/5072

摘要： A layout design method and system for a semiconductor integrated circuit improves circuit performances related to operated frequency and power consumption by improved placement and routing. The method features an intersecting wiring predicting step that predicts the number of the intersecting wirings based on predicted wiring routes and an intersecting wiring capacitance calculating step that calculates the capacitances between the intersecting wirings.

摘要翻译： 半导体集成电路的布局设计方法和系统通过改进放置和布线来改善与操作频率和功耗有关的电路性能。 该方法具有基于预测的布线路径预测相交布线的数量的交叉布线预测步骤和计算交叉布线之间的电容的交叉布线电容计算步骤。

公开(公告)号：US5801960A

公开(公告)日：1998-09-01

申请号：US963311

申请日：1997-11-03

申请人： Midori Takano ,  Fumihiro Minami ,  Mutsunori Igarashi

发明人： Midori Takano ,  Fumihiro Minami ,  Mutsunori Igarashi

IPC分类号： H01L21/82 ,  G06F17/50

CPC分类号： G06F17/5077

摘要： A layout method of designing a wiring pattern on a semiconductor integrated circuit chip according to the present invention comprises three steps of omitting a part of or all of a wiring pattern within cells for a plurality of circuit elements for layout results of these predetermined circuit elements to prepare wiring obstruction data (step 1); deciding a specific wiring path connecting between the cells with reference to the prepared wiring obstruction data (step 2); and repositioning of the cell to correct the layout with no design rule violation and no short between this specific wiring path and the wiring pattern within cells (step 3). The pattern layout is performed so that the specific wiring path is wired in the shortest length of wiring path without making a snaking wire path and also uncomplete wiring does not happen to occur.

摘要翻译： 根据本发明的在半导体集成电路芯片上设计布线图案的布置方法包括以下三个步骤：省略用于多个电路元件的单元内的布线图案的一部分或全部，用于将这些预定电路元件的布局结果 准备接线障碍物数据（步骤1）; 参照准备好的布线障碍物数据确定连接单元之间的具体布线路径（步骤2）; 并且重新定位单元以校正布局，而没有设计规则违反，并且在该特定布线路径和单元内的布线图案之间没有短路（步骤3）。 执行图案布局，使得特定布线路径布线在布线路径的最短长度中，而不会产生蛇线路，并且也不会发生不完全布线。